| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-01-21 | Update DSP wrapper instance names. | Pavel V. Shatov (Meister) |
| 2019-10-23 | Added missing copyright headers. | Pavel V. Shatov (Meister) |
| 2019-10-21 | Reworked testbench, clk_sys and clk_core can now have any ratio, not | Pavel V. Shatov (Meister) |
| 2019-10-21 | Further work: | Pavel V. Shatov (Meister) |
| 2019-10-21 | Redesigned the testbench. Core clock does not necessarily need to be twice | Pavel V. Shatov (Meister) |
| 2019-10-03 | Added more micro-operations, also added "general worker" module. The worker i... | Pavel V. Shatov (Meister) |
| 2019-10-01 | Redesigned core architecture, unified bank structure. All storage blocks now | Pavel V. Shatov (Meister) |
| 2019-10-01 | Major rewrite (different core hierarchy, buses, wrappers, etc). | Pavel V. Shatov (Meister) |
 |
index : user/shatov/modexpng | |
| "Next-generation" modular exponentiation using the specialized DSP slices present in the Artix-7 FPGA | git repositories |
| aboutsummaryrefslogtreecommitdiff |