diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 15:19:30 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2019-10-21 15:19:30 +0300 |
| commit | edd5efd83266bb534d7cde3d908e74749278ed96 (patch) | |
| tree | c7b5295fc73f1904d9206630ca1eee897ba05cdc /rtl/modexpng_dsp_array_block.v | |
| parent | 584393ac5fc9bbe80887702ec2fc97bee999c5e7 (diff) | |
Reworked testbench, clk_sys and clk_core can now have any ratio, not
necessarily 1:2.
Fixed compile-time issue where ISE fails to place two DSP slices next to each
other, if A and/or B cascade path(s) between then are partially connected.
Basically, if cascade is used, entire bus must be connected.
Diffstat (limited to 'rtl/modexpng_dsp_array_block.v')
| -rw-r--r-- | rtl/modexpng_dsp_array_block.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/rtl/modexpng_dsp_array_block.v b/rtl/modexpng_dsp_array_block.v index 1444aa7..2724a68 100644 --- a/rtl/modexpng_dsp_array_block.v +++ b/rtl/modexpng_dsp_array_block.v @@ -24,8 +24,8 @@ module modexpng_dsp_array_block input [ WORD_W -1:0] b; output [NUM_MULTS_AUX * MAC_W -1:0] p; - wire [WORD_EXT_W -1:0] casc_a[0:NUM_MULTS_HALF-1]; - wire [ WORD_W -1:0] casc_b[0:NUM_MULTS_HALF-1]; + wire [DSP48E1_A_W -1:0] casc_a[0:NUM_MULTS_HALF-1]; + wire [DSP48E1_B_W -1:0] casc_b[0:NUM_MULTS_HALF-1]; wire ce_a0 = ce_a; reg ce_a1 = 1'b0; @@ -70,8 +70,8 @@ module modexpng_dsp_array_block .opmode ({1'b0, mode_z[2*z], 1'b0, 2'b01, 2'b01}), .alumode ({DSP48E1_ALUMODE_W{1'b0}}), - .casc_a_in (WORD_EXT_ZERO), - .casc_b_in (WORD_ZERO), + .casc_a_in (), + .casc_b_in (), .casc_a_out (casc_a[z]), .casc_b_out (casc_b[z]) @@ -138,8 +138,8 @@ module modexpng_dsp_array_block .opmode ({1'b0, mode_z[2*NUM_MULTS_HALF], 1'b0, 2'b01, 2'b01}), .alumode ({DSP48E1_ALUMODE_W{1'b0}}), - .casc_a_in (WORD_EXT_ZERO), - .casc_b_in (WORD_ZERO), + .casc_a_in (), + .casc_b_in (), .casc_a_out (), .casc_b_out () |