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path: root/rtl/modexpng_dsp_array_block.v
AgeCommit message (Expand)Author
2019-10-21Reworked testbench, clk_sys and clk_core can now have any ratio, notPavel V. Shatov (Meister)
2019-10-21Further work:Pavel V. Shatov (Meister)
2019-10-21Redesigned the testbench. Core clock does not necessarily need to be twicePavel V. Shatov (Meister)
2019-10-03Added more micro-operations, also added "general worker" module. The worker i...Pavel V. Shatov (Meister)
2019-10-01Redesigned core architecture, unified bank structure. All storage blocks nowPavel V. Shatov (Meister)
2019-10-01Major rewrite (different core hierarchy, buses, wrappers, etc).Pavel V. Shatov (Meister)