diff options
Diffstat (limited to 'bench')
| -rw-r--r-- | bench/tb_core_full_1024.v | 52 | ||||
| -rw-r--r-- | bench/tb_core_full_512.v | 13 | ||||
| -rw-r--r-- | bench/tb_mmm_dual_x8.v | 102 | ||||
| -rw-r--r-- | bench/tb_wrapper.v | 20 |
4 files changed, 131 insertions, 56 deletions
diff --git a/bench/tb_core_full_1024.v b/bench/tb_core_full_1024.v index 87eac79..90e3ae9 100644 --- a/bench/tb_core_full_1024.v +++ b/bench/tb_core_full_1024.v @@ -300,18 +300,16 @@ module tb_core_full_1024; sync_clk_bus; // switch to slow bus clock core_set_input; // write to core input banks - //sync_clk; // switch to fast core clock - //core_set_crt_mode(1); // enable CRT signing - //core_pulse_next; // assert 'next' bit for one cycle - //core_wait_valid; // wait till 'valid' bit gets asserted - - //sync_clk_bus; // switch to slow bus clock - //core_get_output; // read from core output banks - //core_verify_output; // check, whether core output matches precomputed known good refrence values - - bit_index_last_n = 16; - bus_write(2'd2, BANK_IN_2_D, 7'd0, 32'h00010001); - + sync_clk; // switch to fast core clock + core_set_crt_mode(1); // enable CRT signing + core_pulse_next; // assert 'next' bit for one cycle + core_wait_valid; // wait till 'valid' bit gets asserted + + sync_clk_bus; // switch to slow bus clock + core_get_output; // read from core output banks + core_verify_output; // check, whether core output matches precomputed known good refrence values + core_print_load; // + sync_clk; // switch to fast core clock core_set_crt_mode(0); // disable CRT signing core_pulse_next; // assert 'next' bit for one cycle @@ -320,6 +318,7 @@ module tb_core_full_1024; sync_clk_bus; // switch to slow bus clock core_get_output; // read from core output banks core_verify_output; // check, whether core output matches precomputed known good refrence values + core_print_load; // end endtask @@ -592,4 +591,33 @@ module tb_core_full_1024; endtask + // + // Multiplier Load Calculator + // + real load_cyc_total_prev = 0.0; + real load_cyc_mult_prev = 0.0; + + real load_cyc_total = 0.0; + + always @(posedge clk) + // + if (!core_valid) + load_cyc_total <= load_cyc_total + 1.0; + + task core_print_load; + real delta_cyc_total, delta_cyc_mult, load_pct; + begin + `ifndef MODEXPNG_ENABLE_DEBUG + $display("core_print_load: Multiplier load was not calculated, since MODEXPNG_ENABLE_DEBUG was no defined."); + `else + delta_cyc_total = load_cyc_total - load_cyc_total_prev; + delta_cyc_mult = uut.mmm_x.load_cyc_mult - load_cyc_mult_prev; + load_pct = 100.0 * delta_cyc_mult / delta_cyc_total; + $display("Multiplier load: %.1f%%", load_pct); + load_cyc_total_prev = load_cyc_total; + load_cyc_mult_prev = uut.mmm_x.load_cyc_mult; + `endif + end + endtask + endmodule diff --git a/bench/tb_core_full_512.v b/bench/tb_core_full_512.v index 6357d4e..b4bdfb3 100644 --- a/bench/tb_core_full_512.v +++ b/bench/tb_core_full_512.v @@ -177,7 +177,7 @@ module tb_core_full_512; wire [ 1:0] bus_addr_sel = bus_addr[11:10]; wire [ 2:0] bus_addr_bank = bus_addr[9:7]; wire [ 6:0] bus_addr_data = bus_addr[6:0]; - + // // UUT @@ -531,4 +531,15 @@ module tb_core_full_512; endtask + // + // Multiplier Load Calculator + // + integer cyc_total = 0; + + always @(posedge clk) + // + if (!core_valid) + cyc_total <= cyc_total + 1'b1; + + endmodule diff --git a/bench/tb_mmm_dual_x8.v b/bench/tb_mmm_dual_x8.v index 7e54d09..1188f92 100644 --- a/bench/tb_mmm_dual_x8.v +++ b/bench/tb_mmm_dual_x8.v @@ -7,7 +7,6 @@ module tb_mmm_dual_x8; // Headers // `include "../rtl/modexpng_parameters.vh" - //`include "../rtl_1/modexpng_mmm_fsm_old.vh" // @@ -352,7 +351,7 @@ module tb_mmm_dual_x8; modexpng_mmm_dual uut ( .clk (clk), - .rst (rst), + .rst_n (~rst), .ena (ena), .rdy (rdy), @@ -362,6 +361,7 @@ module tb_mmm_dual_x8; .word_index_last_minus1 (word_index_last_minus1), .force_unity_b (1'b0), .only_reduce (1'b0), + .just_multiply (1'b0), .sel_wide_in (BANK_WIDE_A), .sel_narrow_in (BANK_NARROW_A), @@ -372,16 +372,16 @@ module tb_mmm_dual_x8; .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux), .rd_wide_xy_addr (rd_wide_xy_addr), .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux), - .rd_wide_x_dout (rd_wide_x_dout), - .rd_wide_y_dout (rd_wide_y_dout), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux), + .rd_wide_x_din (rd_wide_x_dout), + .rd_wide_y_din (rd_wide_y_dout), + .rd_wide_x_din_aux (rd_wide_x_dout_aux), + .rd_wide_y_din_aux (rd_wide_y_dout_aux), .rd_narrow_xy_ena (rd_narrow_xy_ena), .rd_narrow_xy_bank (rd_narrow_xy_bank), .rd_narrow_xy_addr (rd_narrow_xy_addr), - .rd_narrow_x_dout (rd_narrow_x_dout), - .rd_narrow_y_dout (rd_narrow_y_dout), + .rd_narrow_x_din (rd_narrow_x_dout), + .rd_narrow_y_din (rd_narrow_y_dout), .rcmb_wide_xy_bank (rcmb_wide_xy_bank), .rcmb_wide_xy_addr (rcmb_wide_xy_addr), @@ -412,7 +412,7 @@ module tb_mmm_dual_x8; modexpng_reductor reductor ( .clk (clk), - .rst (rst), + .rst_n (~rst), .ena (rdct_ena), .rdy (rdct_rdy), @@ -422,15 +422,13 @@ module tb_mmm_dual_x8; .sel_wide_out (BANK_WIDE_B), .sel_narrow_out (BANK_NARROW_B), - .rd_wide_xy_addr_aux (rd_wide_xy_addr_aux), - .rd_wide_xy_bank_aux (rd_wide_xy_bank_aux), - .rd_wide_x_dout_aux (rd_wide_x_dout_aux), - .rd_wide_y_dout_aux (rd_wide_y_dout_aux), + .rd_wide_x_din_aux (rd_wide_x_dout_aux), + .rd_wide_y_din_aux (rd_wide_y_dout_aux), .rcmb_final_xy_bank (rcmb_final_xy_bank), .rcmb_final_xy_addr (rcmb_final_xy_addr), - .rcmb_final_x_dout (rcmb_final_x_dout), - .rcmb_final_y_dout (rcmb_final_y_dout), + .rcmb_final_x_din (rcmb_final_x_dout), + .rcmb_final_y_din (rcmb_final_y_dout), .rcmb_final_xy_valid (rcmb_final_xy_valid), .rdct_wide_xy_bank (rdct_wide_xy_bank), @@ -452,7 +450,7 @@ module tb_mmm_dual_x8; modexpng_storage_block storage_block ( .clk (clk), - .rst (rst), + .rst_n (~rst), .wr_wide_xy_ena (wr_wide_xy_ena), .wr_wide_xy_bank (wr_wide_xy_bank), @@ -481,37 +479,49 @@ module tb_mmm_dual_x8; .rd_narrow_xy_bank (rd_narrow_xy_bank), .rd_narrow_xy_addr (rd_narrow_xy_addr), .rd_narrow_x_dout (rd_narrow_x_dout), - .rd_narrow_y_dout (rd_narrow_y_dout) + .rd_narrow_y_dout (rd_narrow_y_dout), + + .wrk_wide_xy_ena (1'b0), + .wrk_wide_xy_bank (), + .wrk_wide_xy_addr (), + .wrk_wide_x_dout (), + .wrk_wide_y_dout (), + + .wrk_narrow_xy_ena (1'b0), + .wrk_narrow_xy_bank (), + .wrk_narrow_xy_addr (), + .wrk_narrow_x_dout (), + .wrk_narrow_y_dout () ); modexpng_storage_manager storage_manager ( .clk (clk), - .rst (rst), + .rst_n (~rst), .wr_wide_xy_ena (wr_wide_xy_ena), .wr_wide_xy_bank (wr_wide_xy_bank), .wr_wide_xy_addr (wr_wide_xy_addr), - .wr_wide_x_din (wr_wide_x_din), - .wr_wide_y_din (wr_wide_y_din), + .wr_wide_x_dout (wr_wide_x_din), + .wr_wide_y_dout (wr_wide_y_din), .wr_narrow_xy_ena (wr_narrow_xy_ena), .wr_narrow_xy_bank (wr_narrow_xy_bank), .wr_narrow_xy_addr (wr_narrow_xy_addr), - .wr_narrow_x_din (wr_narrow_x_din), - .wr_narrow_y_din (wr_narrow_y_din), + .wr_narrow_x_dout (wr_narrow_x_din), + .wr_narrow_y_dout (wr_narrow_y_din), - .ext_wide_xy_ena (ext_wide_xy_ena), - .ext_wide_xy_bank (ext_wide_xy_bank), - .ext_wide_xy_addr (ext_wide_xy_addr), - .ext_wide_x_din (ext_wide_x_din), - .ext_wide_y_din (ext_wide_y_din), - - .ext_narrow_xy_ena (ext_narrow_xy_ena), - .ext_narrow_xy_bank (ext_narrow_xy_bank), - .ext_narrow_xy_addr (ext_narrow_xy_addr), - .ext_narrow_x_din (ext_narrow_x_din), - .ext_narrow_y_din (ext_narrow_y_din), + .io_wide_xy_ena (ext_wide_xy_ena), + .io_wide_xy_bank (ext_wide_xy_bank), + .io_wide_xy_addr (ext_wide_xy_addr), + .io_wide_x_din (ext_wide_x_din), + .io_wide_y_din (ext_wide_y_din), + + .io_narrow_xy_ena (ext_narrow_xy_ena), + .io_narrow_xy_bank (ext_narrow_xy_bank), + .io_narrow_xy_addr (ext_narrow_xy_addr), + .io_narrow_x_din (ext_narrow_x_din), + .io_narrow_y_din (ext_narrow_y_din), .rcmb_wide_xy_bank (rcmb_wide_xy_bank), .rcmb_wide_xy_addr (rcmb_wide_xy_addr), @@ -523,7 +533,31 @@ module tb_mmm_dual_x8; .rcmb_narrow_xy_addr (rcmb_narrow_xy_addr), .rcmb_narrow_x_din (rcmb_narrow_x_dout), .rcmb_narrow_y_din (rcmb_narrow_y_dout), - .rcmb_narrow_xy_ena (rcmb_narrow_xy_valid) + .rcmb_narrow_xy_ena (rcmb_narrow_xy_valid), + + .rdct_wide_xy_bank (), + .rdct_wide_xy_addr (), + .rdct_wide_x_din (), + .rdct_wide_y_din (), + .rdct_wide_xy_valid (1'b0), + + .rdct_narrow_xy_bank (), + .rdct_narrow_xy_addr (), + .rdct_narrow_x_din (), + .rdct_narrow_y_din (), + .rdct_narrow_xy_valid (1'b0), + + .wrk_wide_xy_ena (1'b0), + .wrk_wide_xy_bank (), + .wrk_wide_xy_addr (), + .wrk_wide_x_din (), + .wrk_wide_y_din (), + + .wrk_narrow_xy_ena (1'b0), + .wrk_narrow_xy_bank (), + .wrk_narrow_xy_addr (), + .wrk_narrow_x_din (), + .wrk_narrow_y_din () ); diff --git a/bench/tb_wrapper.v b/bench/tb_wrapper.v index 0c51228..e8eacd1 100644 --- a/bench/tb_wrapper.v +++ b/bench/tb_wrapper.v @@ -58,7 +58,7 @@ module tb_wrapper; .clk (clk_bus), .rst_n (rst_n), - .clk_core (clk_bus), + .clk_core (clk), .cs (bus_cs), .we (bus_we), @@ -87,6 +87,8 @@ module tb_wrapper; rst_n = 1'b1; wait_clk_bus_ticks(100); + // use the following code to observe how the core handles invalid parameter settings... + /* bus_read('h11, to); $display("modulus_bits = %0d", to); ti = 100; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); @@ -96,7 +98,6 @@ module tb_wrapper; ti = 513; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 514; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); - ti = 1022; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 1023; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 1024; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); @@ -104,12 +105,11 @@ module tb_wrapper; ti = 1026; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 4094; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); - ti = 4095; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);*/ - ti = 4096; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to);/* + ti = 4095; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); + ti = 4096; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 4097; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); ti = 4098; bus_write('h11, ti); bus_read('h11, to); $display("modulus_bits = %0d -> %0d", ti, to); - bus_read('h12, to); $display("exponent_bits = %0d", to); ti = 0; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); ti = 1; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); @@ -136,11 +136,13 @@ module tb_wrapper; ti = 1026; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); ti = 4094; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); - ti = 4095; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);*/ - ti = 4096; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);/* + ti = 4095; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); + ti = 4096; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); ti = 4097; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); - ti = 4098; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to); - */ + ti = 4098; bus_write('h12, ti); bus_read('h12, to); $display("exponent_bits = %0d -> %0d", ti, to);*/ + + // use the following to observe how the core handles "next" bit rising edge + //ti = 0; bus_write('h08, ti); //ti = 2; bus_write('h08, ti); //ti = 0; bus_write('h08, ti); |