diff options
Diffstat (limited to 'bench/tb_core_full_1024.v')
| -rw-r--r-- | bench/tb_core_full_1024.v | 52 |
1 files changed, 40 insertions, 12 deletions
diff --git a/bench/tb_core_full_1024.v b/bench/tb_core_full_1024.v index 87eac79..90e3ae9 100644 --- a/bench/tb_core_full_1024.v +++ b/bench/tb_core_full_1024.v @@ -300,18 +300,16 @@ module tb_core_full_1024; sync_clk_bus; // switch to slow bus clock core_set_input; // write to core input banks - //sync_clk; // switch to fast core clock - //core_set_crt_mode(1); // enable CRT signing - //core_pulse_next; // assert 'next' bit for one cycle - //core_wait_valid; // wait till 'valid' bit gets asserted - - //sync_clk_bus; // switch to slow bus clock - //core_get_output; // read from core output banks - //core_verify_output; // check, whether core output matches precomputed known good refrence values - - bit_index_last_n = 16; - bus_write(2'd2, BANK_IN_2_D, 7'd0, 32'h00010001); - + sync_clk; // switch to fast core clock + core_set_crt_mode(1); // enable CRT signing + core_pulse_next; // assert 'next' bit for one cycle + core_wait_valid; // wait till 'valid' bit gets asserted + + sync_clk_bus; // switch to slow bus clock + core_get_output; // read from core output banks + core_verify_output; // check, whether core output matches precomputed known good refrence values + core_print_load; // + sync_clk; // switch to fast core clock core_set_crt_mode(0); // disable CRT signing core_pulse_next; // assert 'next' bit for one cycle @@ -320,6 +318,7 @@ module tb_core_full_1024; sync_clk_bus; // switch to slow bus clock core_get_output; // read from core output banks core_verify_output; // check, whether core output matches precomputed known good refrence values + core_print_load; // end endtask @@ -592,4 +591,33 @@ module tb_core_full_1024; endtask + // + // Multiplier Load Calculator + // + real load_cyc_total_prev = 0.0; + real load_cyc_mult_prev = 0.0; + + real load_cyc_total = 0.0; + + always @(posedge clk) + // + if (!core_valid) + load_cyc_total <= load_cyc_total + 1.0; + + task core_print_load; + real delta_cyc_total, delta_cyc_mult, load_pct; + begin + `ifndef MODEXPNG_ENABLE_DEBUG + $display("core_print_load: Multiplier load was not calculated, since MODEXPNG_ENABLE_DEBUG was no defined."); + `else + delta_cyc_total = load_cyc_total - load_cyc_total_prev; + delta_cyc_mult = uut.mmm_x.load_cyc_mult - load_cyc_mult_prev; + load_pct = 100.0 * delta_cyc_mult / delta_cyc_total; + $display("Multiplier load: %.1f%%", load_pct); + load_cyc_total_prev = load_cyc_total; + load_cyc_mult_prev = uut.mmm_x.load_cyc_mult; + `endif + end + endtask + endmodule |