Added two pairs of new wrappers.

4 files changed, 681 insertions, 0 deletions

diff --git a/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v b/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v
new file mode 100644
index 0000000..0ef45fe
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_addsub_wrapper_generic.v
@@ -0,0 +1,224 @@
+//======================================================================
+//
+// Copyright (c) 2019, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpng_dsp_slice_addsub_wrapper_generic
+(
+    clk,
+    ce_abc,
+    ce_p,
+    ce_ctrl,
+    x, y, p,
+    op_mode,
+    alu_mode,
+    carry_in_sel,
+    casc_p_in,
+    casc_p_out,
+    carry_out
+);
+
+    `include "modexpng_dsp48e1.vh"
+
+    input                              clk;
+    input                              ce_abc;
+    input                              ce_p;
+    input                              ce_ctrl;
+    input  [         DSP48E1_C_W -1:0] x;
+    input  [         DSP48E1_C_W -1:0] y;
+    output [         DSP48E1_P_W -1:0] p;
+    input  [    DSP48E1_OPMODE_W -1:0] op_mode;
+    input  [   DSP48E1_ALUMODE_W -1:0] alu_mode;
+    input  [DSP48E1_CARRYINSEL_W -1:0] carry_in_sel;
+    input  [         DSP48E1_P_W -1:0] casc_p_in;
+    output [         DSP48E1_P_W -1:0] casc_p_out;
+    output                             carry_out;
+
+
+    //
+    // Internal Registers
+    //
+    reg [         DSP48E1_C_W -1:0] reg_x;
+    reg [         DSP48E1_C_W -1:0] reg_y;
+
+    reg [    DSP48E1_OPMODE_W -1:0] reg_op_mode;
+    reg [   DSP48E1_ALUMODE_W -1:0] reg_alu_mode;
+    reg [DSP48E1_CARRYINSEL_W -1:0] reg_carry_in_sel;
+
+    always @(posedge clk)
+        //
+        if (ce_abc) begin
+            reg_x <= x;
+            reg_y <= y;
+        end
+        
+    always @(posedge clk)
+        //
+        if (ce_ctrl) begin
+            reg_op_mode      <= op_mode;
+            reg_alu_mode     <= alu_mode;
+            reg_carry_in_sel <= carry_in_sel;
+        end
+
+
+    //
+    // Generic Math Slice Model
+    //
+    function  [DSP48E1_C_W-1:0] calc_mux_x;
+        input [            1:0] opmode_x;
+        input [DSP48E1_C_W-1:0] ab_value;
+        case (opmode_x)
+            DSP48E1_OPMODE_X_0:  calc_mux_x = {DSP48E1_C_W{1'b0}};
+            DSP48E1_OPMODE_X_AB: calc_mux_x = ab_value;
+            default: begin
+                $display("ERROR: Bad X opmode (%b)!", opmode_x);
+                $finish;
+            end
+        endcase
+    endfunction
+
+    function  [DSP48E1_C_W-1:0] calc_mux_y;
+        input [            1:0] opmode_y;
+        input [DSP48E1_C_W-1:0] c_value;
+        case (opmode_y)
+            DSP48E1_OPMODE_Y_0: calc_mux_y = {DSP48E1_C_W{1'b0}};
+            DSP48E1_OPMODE_Y_C: calc_mux_y = c_value;
+            default: begin
+                $display("ERROR: Bad Y opmode (%b)!", opmode_y);
+                $finish;
+            end
+        endcase
+    endfunction
+
+    function  [DSP48E1_C_W-1:0] calc_mux_z;
+        input [            2:0] opmode_z;
+        input [DSP48E1_P_W-1:0] p_value;
+        input [DSP48E1_C_W-1:0] c_value;
+        input [DSP48E1_P_W-1:0] pcin_value;
+        case (opmode_z)
+            DSP48E1_OPMODE_Z_0:      calc_mux_z = {DSP48E1_C_W{1'b0}};                        // 000
+            DSP48E1_OPMODE_Z_C:      calc_mux_z = c_value;                                    // 011
+            DSP48E1_OPMODE_Z_PCIN17: calc_mux_z = {{17{1'b0}}, pcin_value[DSP48E1_C_W-1:17]}; // 101
+            DSP48E1_OPMODE_Z_P17:    calc_mux_z = {{17{1'b0}}, p_value[DSP48E1_C_W-1:17]};    // 110
+            default: begin
+                $display("ERROR: Bad Z opmode (%b)!", opmode_z);
+                $finish;
+            end
+        endcase
+    endfunction
+
+    function  [         DSP48E1_C_W -1:0] calc_mux_cin;
+        input [DSP48E1_CARRYINSEL_W -1:0] carryinsel_value;
+        input [   DSP48E1_ALUMODE_W -1:0] alumode_value;
+        input                             carry_value;
+        case (carryinsel_value)
+            DSP48E1_CARRYINSEL_CARRYIN: calc_mux_cin = 1'b0; // 000
+            DSP48E1_CARRYINSEL_CARRYCASCOUT: // 100
+                case (alumode_value)
+                    DSP48E1_ALUMODE_Z_PLUS_X_AND_Y_AND_CIN:  calc_mux_cin = carry_value; 
+                    DSP48E1_ALUMODE_Z_MINUS_X_AND_Y_AND_CIN: calc_mux_cin = ~carry_value;
+                    default: begin
+                        $display("ERROR: Invalid ALUMODE (%b)!", alumode_value);
+                        $finish;
+                    end
+                endcase
+            default: begin
+                $display("ERROR: Bad CARRYINSEL (%b)!", carryinsel_value);
+                $finish;
+            end
+        endcase
+    endfunction
+    
+    function  [         DSP48E1_P_W   :0] calc_p;
+        input [   DSP48E1_ALUMODE_W -1:0] alumode_value;
+        input [    DSP48E1_OPMODE_W -1:0] opmode_value;
+        input [DSP48E1_CARRYINSEL_W -1:0] carryinsel_value;
+        input [         DSP48E1_P_W -1:0] p_value;
+        input [         DSP48E1_C_W -1:0] ab_value;
+        input [         DSP48E1_C_W -1:0] c_value;
+        input                             carry_value;
+        input [         DSP48E1_P_W -1:0] pcin_value;
+        reg   [         DSP48E1_C_W -1:0] mux_x;
+        reg   [         DSP48E1_C_W -1:0] mux_y;
+        reg   [         DSP48E1_C_W -1:0] mux_z;
+        reg                               mux_cin;
+        reg   [         DSP48E1_P_W   :0] int_p;
+        begin
+            mux_x   = calc_mux_x(opmode_value[1:0], ab_value);
+            mux_y   = calc_mux_y(opmode_value[3:2], c_value);
+            mux_z   = calc_mux_z(opmode_value[6:4], p_value, c_value, pcin_value);
+            mux_cin = calc_mux_cin(carryinsel_value, alumode_value, carry_value);
+            case (alumode_value)
+                //
+                DSP48E1_ALUMODE_Z_PLUS_X_AND_Y_AND_CIN: begin
+                    int_p = {1'b0, mux_z} + {1'b0, mux_x} + {1'b0, mux_y} + {{DSP48E1_P_W{1'b0}}, mux_cin};
+                    calc_p = {int_p[DSP48E1_P_W], int_p[DSP48E1_P_W-1:0]};
+                end
+                //  
+                DSP48E1_ALUMODE_Z_MINUS_X_AND_Y_AND_CIN: begin
+                    int_p = {1'b0, mux_z} - {1'b0, mux_x} - {1'b0, mux_y} - {{DSP48E1_P_W{1'b0}}, mux_cin};
+                    calc_p = {~int_p[DSP48E1_P_W], int_p[DSP48E1_P_W-1:0]};
+                end
+                //
+                default: begin
+                    $display("ERROR: Invalid ALUMODE (%b)!", alumode_value);
+                    $finish;
+                end
+            endcase
+        end
+    endfunction
+
+
+    //
+    // Output Registers
+    //
+    reg [DSP48E1_P_W -1:0] reg_p;
+    reg                    reg_carry_out;
+    
+    always @(posedge clk)
+        //
+        if (ce_p) {reg_carry_out, reg_p} <=
+            calc_p(reg_alu_mode, reg_op_mode, reg_carry_in_sel, reg_p, reg_x, reg_y, reg_carry_out, casc_p_in);
+
+
+    //
+    // Output Buses
+    //
+    assign p = reg_p;
+    assign carry_out = reg_carry_out;
+    
+
+    //
+    // Cascade Bus
+    //
+    assign casc_p_out = reg_p;
+    
+
+endmodule
diff --git a/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
new file mode 100644
index 0000000..fee8216
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v
@@ -0,0 +1,168 @@
+//======================================================================
+//
+// Copyright (c) 2019, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpng_dsp_slice_addsub_wrapper_xilinx
+(
+    clk,
+    ce_abc,
+    ce_p,
+    ce_ctrl,
+    x, y, p,
+    op_mode,
+    alu_mode,
+    carry_in_sel,
+    casc_p_in,
+    casc_p_out,
+    carry_out
+);
+
+    `include "modexpng_dsp48e1.vh"
+        
+    input                              clk;
+    input                              ce_abc;
+    input                              ce_p;
+    input                              ce_ctrl;
+    input  [         DSP48E1_C_W -1:0] x;
+    input  [         DSP48E1_C_W -1:0] y;
+    output [         DSP48E1_P_W -1:0] p;
+    input  [    DSP48E1_OPMODE_W -1:0] op_mode;
+    input  [   DSP48E1_ALUMODE_W -1:0] alu_mode;
+    input  [DSP48E1_CARRYINSEL_W -1:0] carry_in_sel;
+    input  [         DSP48E1_P_W -1:0] casc_p_in;
+    output [         DSP48E1_P_W -1:0] casc_p_out;
+    output                             carry_out;
+
+    wire [       DSP48E1_A_W -1:0] a_int;
+    wire [       DSP48E1_B_W -1:0] b_int;
+    wire [       DSP48E1_C_W -1:0] c_int;
+    wire [       DSP48E1_P_W -1:0] p_int;
+    wire [DSP48E1_CARRYOUT_W -1:0] carry_out_int;
+
+    assign {a_int, b_int} = {x};
+    assign {c_int}        = {y};
+    assign {p}            = {p_int};
+    assign {carry_out}    = {carry_out_int[DSP48E1_CARRYOUT_W-1]};
+
+    DSP48E1 #
+    (
+        .AREG                   (1),
+        .BREG                   (1),
+        .CREG                   (1),
+        .DREG                   (0),
+        .ADREG                  (0),
+        .MREG                   (0),
+        .PREG                   (1),
+        .ACASCREG               (1),
+        .BCASCREG               (1),
+        .INMODEREG              (0),
+        .OPMODEREG              (1),
+        .ALUMODEREG             (1),
+        .CARRYINREG             (0),
+        .CARRYINSELREG          (1),
+
+        .A_INPUT                ("DIRECT"),
+        .B_INPUT                ("DIRECT"),
+
+        .USE_DPORT              ("FALSE"),
+        .USE_MULT               ("NONE"),
+        .USE_SIMD               ("ONE48"),
+
+        .MASK                   ({DSP48E1_P_W{1'b1}}),
+        .PATTERN                ({DSP48E1_P_W{1'b0}}),
+        .SEL_MASK               ("MASK"),
+        .SEL_PATTERN            ("PATTERN"),
+        
+        .USE_PATTERN_DETECT     ("NO_PATDET"),
+        .AUTORESET_PATDET       ("NO_RESET")
+    )
+    DSP48E1_inst
+    (
+        .CLK                (clk),
+    
+        .CEA1               (1'b0),
+        .CEB1               (1'b0),
+        .CEA2               (ce_abc),
+        .CEB2               (ce_abc),
+        .CEAD               (1'b0),
+        .CEC                (ce_abc),
+        .CED                (1'b0),
+        .CEM                (1'b0),
+        .CEP                (ce_p),
+        .CEINMODE           (1'b0),
+        .CECTRL             (ce_ctrl),
+        .CEALUMODE          (ce_ctrl),
+        .CECARRYIN          (1'b0),
+
+        .A                  (a_int),
+        .B                  (b_int),
+        .C                  (c_int),
+        .D                  ({DSP48E1_D_W{1'b0}}),
+        .P                  (p_int),
+        
+        .INMODE             ({DSP48E1_INMODE_W{1'b0}}),
+        .OPMODE             (op_mode),
+        .ALUMODE            (alu_mode),
+
+        .ACIN               (),
+        .BCIN               (),
+        .ACOUT              (),
+        .BCOUT              (),
+        .PCIN               (casc_p_in),
+        .PCOUT              (casc_p_out),
+        .CARRYCASCIN        (1'b0),
+        .CARRYCASCOUT       (),
+ 
+        .RSTA               (1'b0),
+        .RSTB               (1'b0),
+        .RSTC               (1'b0),
+        .RSTD               (1'b0),
+        .RSTM               (1'b0),
+        .RSTP               (1'b0),
+        .RSTINMODE          (1'b0),
+        .RSTCTRL            (1'b0),
+        .RSTALUMODE         (1'b0),
+        .RSTALLCARRYIN      (1'b0),
+
+        .UNDERFLOW          (),
+        .OVERFLOW           (),
+        .PATTERNDETECT      (),
+        .PATTERNBDETECT     (),
+
+        .CARRYIN            (1'b0),
+        .CARRYOUT           (carry_out_int),
+        .CARRYINSEL         (carry_in_sel),
+
+        .MULTSIGNIN         (1'b0),
+        .MULTSIGNOUT        ()
+    );
+
+endmodule
diff --git a/rtl/modexpng_dsp_slice_mult_wrapper_generic.v b/rtl/modexpng_dsp_slice_mult_wrapper_generic.v
new file mode 100644
index 0000000..524d0dd
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_mult_wrapper_generic.v
@@ -0,0 +1,124 @@
+//======================================================================
+//
+// Copyright (c) 2019, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpng_dsp_slice_mult_wrapper_generic #
+(
+    AB_INPUT   = "DIRECT",
+    B_REG      = 2
+)
+(
+    clk,
+    ce_a1, ce_b1, ce_a2, ce_b2,
+    ce_m, ce_p, ce_mode,
+    a, b, p,
+    inmode, opmode, alumode,
+    casc_a_in,  casc_b_in,
+    casc_a_out, casc_b_out
+);
+
+    `include "modexpng_parameters.vh"
+    `include "modexpng_dsp48e1.vh"
+        
+    input                           clk;            //
+    input                           ce_a1;          //
+    input                           ce_b1;          //
+    input                           ce_a2;          //
+    input                           ce_b2;          //
+    input                           ce_m;           //
+    input                           ce_p;           //
+    input                           ce_mode;        //
+    input  [       WORD_EXT_W -1:0] a;              //
+    input  [           WORD_W -1:0] b;              //
+    output [            MAC_W -1:0] p;              //
+    input  [ DSP48E1_INMODE_W -1:0] inmode;         //
+    input  [ DSP48E1_OPMODE_W -1:0] opmode;         //
+    input  [DSP48E1_ALUMODE_W -1:0] alumode;        //
+    input  [      DSP48E1_A_W -1:0] casc_a_in;      //
+    input  [      DSP48E1_B_W -1:0] casc_b_in;      //
+    output [      DSP48E1_A_W -1:0] casc_a_out;     //
+    output [      DSP48E1_B_W -1:0] casc_b_out;     //
+    
+    //
+    // A Port
+    //
+    wire [WORD_EXT_W -1:0] a_mux = AB_INPUT == "DIRECT" ? a : casc_a_in[WORD_EXT_W-1:0];
+    reg  [WORD_EXT_W -1:0] a_reg1;
+    reg  [WORD_EXT_W -1:0] a_reg2;
+
+    assign casc_a_out = a_reg1;
+
+    always @(posedge clk) begin
+        if (ce_a1) a_reg1 <= a_mux;
+        if (ce_a2) a_reg2 <= a_reg1;
+    end
+    
+    //
+    // B Port
+    //
+    wire [WORD_W -1:0] b_mux = AB_INPUT == "DIRECT" ? b : casc_b_in[WORD_W-1:0];
+    reg  [WORD_W -1:0] b_reg1;
+    reg  [WORD_W -1:0] b_reg2;
+
+    assign casc_b_out = b_reg1;
+
+    always @(posedge clk) begin
+        if (ce_b1) b_reg1 <= b_mux;
+        if (ce_b2) b_reg2 <= B_REG == 2 ? b_reg1 : b_mux;
+    end
+
+    //
+    // OPMODE Port
+    //
+    reg [DSP48E1_OPMODE_W -1:0] opmode_reg;
+    
+    always @(posedge clk) begin
+        if (ce_mode) opmode_reg <= opmode;
+    end
+
+    //
+    // M, P
+    //
+    reg [MAC_W-1:0] m_reg;
+    reg [MAC_W-1:0] p_reg;
+    
+    wire [MAC_W-1:0] a_pad = {{MAC_W-WORD_EXT_W{1'b0}}, a_reg2};
+    wire [MAC_W-1:0] b_pad = {{MAC_W-WORD_W{1'b0}}, b_reg2};
+    wire [MAC_W-1:0] p_pad = opmode_reg[5] ? p_reg : {MAC_W{1'b0}};
+    
+    assign p = p_reg;
+    
+    always @(posedge clk) begin
+        if (ce_m) m_reg <= a_pad * b_pad;
+        if (ce_p) p_reg <= m_reg + p_pad;
+    end
+
+endmodule
diff --git a/rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v b/rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v
new file mode 100644
index 0000000..cd9baf8
--- /dev/null
+++ b/rtl/modexpng_dsp_slice_mult_wrapper_xilinx.v
@@ -0,0 +1,165 @@
+//======================================================================
+//
+// Copyright (c) 2019, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+//   be used to endorse or promote products derived from this software
+//   without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpng_dsp_slice_mult_wrapper_xilinx #
+(
+    AB_INPUT   = "DIRECT",
+    B_REG      = 2
+)
+(
+    clk,
+    ce_a1, ce_b1, ce_a2, ce_b2,
+    ce_m, ce_p, ce_mode,
+    a, b, p,
+    inmode, opmode, alumode,
+    casc_a_in,  casc_b_in,
+    casc_a_out, casc_b_out
+);
+
+    `include "modexpng_parameters.vh"
+    `include "modexpng_dsp48e1.vh"
+        
+    input                           clk;
+    input                           ce_a1;
+    input                           ce_b1;
+    input                           ce_a2;
+    input                           ce_b2;
+    input                           ce_m;
+    input                           ce_p;
+    input                           ce_mode;
+    input  [       WORD_EXT_W -1:0] a;
+    input  [           WORD_W -1:0] b;
+    output [            MAC_W -1:0] p;
+    input  [ DSP48E1_INMODE_W -1:0] inmode;
+    input  [ DSP48E1_OPMODE_W -1:0] opmode;
+    input  [DSP48E1_ALUMODE_W -1:0] alumode;
+    input  [      DSP48E1_A_W -1:0] casc_a_in;
+    input  [      DSP48E1_B_W -1:0] casc_b_in;
+    output [      DSP48E1_A_W -1:0] casc_a_out;
+    output [      DSP48E1_B_W -1:0] casc_b_out;
+    
+    wire [DSP48E1_P_W - MAC_W      -1:0] p_dummy;
+
+    DSP48E1 #
+    (
+        .AREG                   (2),
+        .BREG                   (B_REG),
+        .CREG                   (0),
+        .DREG                   (0),
+        .ADREG                  (0),
+        .MREG                   (1),
+        .PREG                   (1),
+        .ACASCREG               (1),
+        .BCASCREG               (1),
+        .INMODEREG              (0),
+        .OPMODEREG              (1),
+        .ALUMODEREG             (0),
+        .CARRYINREG             (0),
+        .CARRYINSELREG          (0),
+
+        .A_INPUT                (AB_INPUT),
+        .B_INPUT                (AB_INPUT),
+
+        .USE_DPORT              ("FALSE"),
+        .USE_MULT               ("DYNAMIC"),
+        .USE_SIMD               ("ONE48"),
+
+        .MASK                   ({DSP48E1_P_W{1'b1}}),
+        .PATTERN                ({DSP48E1_P_W{1'b0}}),
+        .SEL_MASK               ("MASK"),
+        .SEL_PATTERN            ("PATTERN"),
+        
+        .USE_PATTERN_DETECT     ("NO_PATDET"),
+        .AUTORESET_PATDET       ("NO_RESET")
+    )
+    DSP48E1_inst
+    (
+        .CLK                (clk),
+    
+        .CEA1               (ce_a1),
+        .CEB1               (ce_b1),
+        .CEA2               (ce_a2),
+        .CEB2               (ce_b2),
+        .CEAD               (1'b0),
+        .CEC                (1'b0),
+        .CED                (1'b0),
+        .CEM                (ce_m),
+        .CEP                (ce_p),
+        .CEINMODE           (1'b0),
+        .CECTRL             (ce_mode),
+        .CEALUMODE          (1'b0),
+        .CECARRYIN          (1'b0),
+
+        .A                  ({{(DSP48E1_A_W-WORD_EXT_W){1'b0}}, a}),
+        .B                  ({{(DSP48E1_B_W-WORD_W){1'b0}}, b}),
+        .C                  ({DSP48E1_C_W{1'b0}}),
+        .D                  ({DSP48E1_D_W{1'b0}}),
+        .P                  ({p_dummy, p}),
+        
+        .INMODE             (inmode),
+        .OPMODE             (opmode),
+        .ALUMODE            (alumode),
+
+        .ACIN               (casc_a_in),
+        .BCIN               (casc_b_in),
+        .ACOUT              (casc_a_out),
+        .BCOUT              (casc_b_out),
+        .PCIN               ({DSP48E1_P_W{1'b0}}),
+        .PCOUT              (),
+        .CARRYCASCIN        (1'b0),
+        .CARRYCASCOUT       (),
+ 
+        .RSTA               (1'b0),
+        .RSTB               (1'b0),
+        .RSTC               (1'b0),
+        .RSTD               (1'b0),
+        .RSTM               (1'b0),
+        .RSTP               (1'b0),
+        .RSTINMODE          (1'b0),
+        .RSTCTRL            (1'b0),
+        .RSTALUMODE         (1'b0),
+        .RSTALLCARRYIN      (1'b0),
+
+        .UNDERFLOW          (),
+        .OVERFLOW           (),
+        .PATTERNDETECT      (),
+        .PATTERNBDETECT     (),
+
+        .CARRYIN            (1'b0),
+        .CARRYOUT           (),
+        .CARRYINSEL         (3'b000),
+
+        .MULTSIGNIN         (1'b0),
+        .MULTSIGNOUT        ()
+    );
+
+endmodule