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Diffstat (limited to 'rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v')
| -rw-r--r-- | rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v | 168 |
1 files changed, 168 insertions, 0 deletions
diff --git a/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v new file mode 100644 index 0000000..fee8216 --- /dev/null +++ b/rtl/modexpng_dsp_slice_addsub_wrapper_xilinx.v @@ -0,0 +1,168 @@ +//====================================================================== +// +// Copyright (c) 2019, NORDUnet A/S All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// - Neither the name of the NORDUnet nor the names of its contributors may +// be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//====================================================================== + +module modexpng_dsp_slice_addsub_wrapper_xilinx +( + clk, + ce_abc, + ce_p, + ce_ctrl, + x, y, p, + op_mode, + alu_mode, + carry_in_sel, + casc_p_in, + casc_p_out, + carry_out +); + + `include "modexpng_dsp48e1.vh" + + input clk; + input ce_abc; + input ce_p; + input ce_ctrl; + input [ DSP48E1_C_W -1:0] x; + input [ DSP48E1_C_W -1:0] y; + output [ DSP48E1_P_W -1:0] p; + input [ DSP48E1_OPMODE_W -1:0] op_mode; + input [ DSP48E1_ALUMODE_W -1:0] alu_mode; + input [DSP48E1_CARRYINSEL_W -1:0] carry_in_sel; + input [ DSP48E1_P_W -1:0] casc_p_in; + output [ DSP48E1_P_W -1:0] casc_p_out; + output carry_out; + + wire [ DSP48E1_A_W -1:0] a_int; + wire [ DSP48E1_B_W -1:0] b_int; + wire [ DSP48E1_C_W -1:0] c_int; + wire [ DSP48E1_P_W -1:0] p_int; + wire [DSP48E1_CARRYOUT_W -1:0] carry_out_int; + + assign {a_int, b_int} = {x}; + assign {c_int} = {y}; + assign {p} = {p_int}; + assign {carry_out} = {carry_out_int[DSP48E1_CARRYOUT_W-1]}; + + DSP48E1 # + ( + .AREG (1), + .BREG (1), + .CREG (1), + .DREG (0), + .ADREG (0), + .MREG (0), + .PREG (1), + .ACASCREG (1), + .BCASCREG (1), + .INMODEREG (0), + .OPMODEREG (1), + .ALUMODEREG (1), + .CARRYINREG (0), + .CARRYINSELREG (1), + + .A_INPUT ("DIRECT"), + .B_INPUT ("DIRECT"), + + .USE_DPORT ("FALSE"), + .USE_MULT ("NONE"), + .USE_SIMD ("ONE48"), + + .MASK ({DSP48E1_P_W{1'b1}}), + .PATTERN ({DSP48E1_P_W{1'b0}}), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + + .USE_PATTERN_DETECT ("NO_PATDET"), + .AUTORESET_PATDET ("NO_RESET") + ) + DSP48E1_inst + ( + .CLK (clk), + + .CEA1 (1'b0), + .CEB1 (1'b0), + .CEA2 (ce_abc), + .CEB2 (ce_abc), + .CEAD (1'b0), + .CEC (ce_abc), + .CED (1'b0), + .CEM (1'b0), + .CEP (ce_p), + .CEINMODE (1'b0), + .CECTRL (ce_ctrl), + .CEALUMODE (ce_ctrl), + .CECARRYIN (1'b0), + + .A (a_int), + .B (b_int), + .C (c_int), + .D ({DSP48E1_D_W{1'b0}}), + .P (p_int), + + .INMODE ({DSP48E1_INMODE_W{1'b0}}), + .OPMODE (op_mode), + .ALUMODE (alu_mode), + + .ACIN (), + .BCIN (), + .ACOUT (), + .BCOUT (), + .PCIN (casc_p_in), + .PCOUT (casc_p_out), + .CARRYCASCIN (1'b0), + .CARRYCASCOUT (), + + .RSTA (1'b0), + .RSTB (1'b0), + .RSTC (1'b0), + .RSTD (1'b0), + .RSTM (1'b0), + .RSTP (1'b0), + .RSTINMODE (1'b0), + .RSTCTRL (1'b0), + .RSTALUMODE (1'b0), + .RSTALLCARRYIN (1'b0), + + .UNDERFLOW (), + .OVERFLOW (), + .PATTERNDETECT (), + .PATTERNBDETECT (), + + .CARRYIN (1'b0), + .CARRYOUT (carry_out_int), + .CARRYINSEL (carry_in_sel), + + .MULTSIGNIN (1'b0), + .MULTSIGNOUT () + ); + +endmodule |