path: root/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v

//======================================================================
//
// Copyright (c) 2019, NORDUnet A/S All rights reserved.
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//======================================================================

module modexpng_tdp_36k_x16_x32_wrapper_generic
(
    clk, clk_bus,
    
    ena, wea,
    addra, dina, douta,
    
    enb, regceb,
    addrb, doutb
);


    //
    // Headers
    //
    `include "modexpng_parameters.vh"


    //
    // Ports
    //
    input                                     clk;
    input                                     clk_bus;
    
    input                                     ena;
    input                                     wea;
    input  [BANK_ADDR_W + BUS_OP_ADDR_W -1:0] addra;
    input  [              BUS_DATA_W    -1:0] dina;
    output [              BUS_DATA_W    -1:0] douta;
    
    input                                     enb;
    input                                     regceb;
    input  [BANK_ADDR_W + OP_ADDR_W     -1:0] addrb;
    output [              WORD_W        -1:0] doutb;

    
    //
    // Memory
    //
    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
   
    //
    // Read-Write Port
    //
    reg [BUS_DATA_W -1:0] douta_reg;
    
    assign douta = douta_reg;
    
    always @(posedge clk_bus)
        //
        if (ena) begin
            if (wea) mem[addra] <= dina;
            douta_reg <= mem[addra];
        end
            
    //
    // Read Port
    //
    reg [WORD_W -1:0] doutb_reg1;
    reg [WORD_W -1:0] doutb_reg2;
    
    assign doutb = doutb_reg2;
    
    wire [BUS_DATA_W -1:0] mem_addrb = mem[addrb[BANK_ADDR_W + OP_ADDR_W -1:1]];
    
    wire [    WORD_W -1:0] mem_addrb_msb = mem_addrb[ BUS_DATA_W -1:WORD_W];
    wire [    WORD_W -1:0] mem_addrb_lsb = mem_addrb[     WORD_W -1:     0];
    
    always @(posedge clk)
        //
        if (enb)
            doutb_reg1 <= addrb[0] ? mem_addrb_msb : mem_addrb_lsb;
            
    always @(posedge clk)
        //
        if (regceb)
            doutb_reg2 <= doutb_reg1;
/*    
    //
    // BRAM_TDP_MACRO
    //
    BRAM_TDP_MACRO #
    (
        .DEVICE                 ("7SERIES"),
        .BRAM_SIZE              ("36Kb"),

        .WRITE_WIDTH_A          (BUS_DATA_W),
        .READ_WIDTH_A           (BUS_DATA_W),

        .WRITE_WIDTH_B          (WORD_W),
        .READ_WIDTH_B           (WORD_W),

        .DOA_REG                (0),
        .DOB_REG                (1),

        .WRITE_MODE_A           ("READ_FIRST"),
        .WRITE_MODE_B           ("READ_FIRST"),

        .SRVAL_A                (36'h000000000),
        .SRVAL_B                (36'h000000000),

        .INIT_A                 (36'h000000000),
        .INIT_B                 (36'h000000000),
        
        .INIT_FILE              ("NONE"),
        .SIM_COLLISION_CHECK    ("NONE")
   )
   BRAM_TDP_MACRO_inst
   (
      .RSTA     (1'b0),
      .RSTB     (1'b0),

      .CLKA     (clk_bus),
      .ENA      (ena),
      .REGCEA   (1'b0),
      .WEA      ({4{wea}}),
      .ADDRA    (addra),
      .DIA      (dina),
      .DOA      (douta),

      .CLKB     (clk),
      .ENB      (enb),
      .REGCEB   (regceb),
      .WEB      ({2{1'b0}}),
      .ADDRB    (addrb),
      .DIB      ({WORD_W{1'b0}}),
      .DOB      (doutb)
   );
   */
    
endmodule