Redesigned the testbench. Core clock does not necessarily need to be twice

faster than the bus clock now. It can be the same, or say four times faster.

1 files changed, 43 insertions, 0 deletions

diff --git a/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v b/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v
index 5e69bef..fda7cf6 100644
--- a/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v
+++ b/rtl/modexpng_tdp_36k_x16_x32_wrapper_generic.v
@@ -35,6 +35,48 @@ module modexpng_tdp_36k_x16_x32_wrapper_generic
 
     
     //
+    // Memory
+    //
+    reg [BUS_DATA_W -1:0] mem[0:2**(BANK_ADDR_W+BUS_OP_ADDR_W)-1];
+   
+    //
+    // Read-Write Port
+    //
+    reg [BUS_DATA_W -1:0] douta_reg;
+    
+    assign douta = douta_reg;
+    
+    always @(posedge clk_bus)
+        //
+        if (ena) begin
+            if (wea) mem[addra] <= dina;
+            douta_reg <= mem[addra];
+        end
+            
+    //
+    // Read Port
+    //
+    reg [WORD_W -1:0] doutb_reg1;
+    reg [WORD_W -1:0] doutb_reg2;
+    
+    assign doutb = doutb_reg2;
+    
+    wire [BUS_DATA_W -1:0] mem_addrb = mem[addrb[BANK_ADDR_W + OP_ADDR_W -1:1]];
+    
+    wire [    WORD_W -1:0] mem_addrb_msb = mem_addrb[ BUS_DATA_W -1:WORD_W];
+    wire [    WORD_W -1:0] mem_addrb_lsb = mem_addrb[     WORD_W -1:     0];
+    
+    always @(posedge clk)
+        //
+        if (enb)
+            doutb_reg1 <= addrb[0] ? mem_addrb_msb : mem_addrb_lsb;
+            
+    always @(posedge clk)
+        //
+        if (regceb)
+            doutb_reg2 <= doutb_reg1;
+/*    
+    //
     // BRAM_TDP_MACRO
     //
     BRAM_TDP_MACRO #
@@ -84,5 +126,6 @@ module modexpng_tdp_36k_x16_x32_wrapper_generic
       .DIB      ({WORD_W{1'b0}}),
       .DOB      (doutb)
    );
+   */
     
 endmodule