diff options
author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-18 02:14:27 +0300 |
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committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-18 02:14:27 +0300 |
commit | 2db58a7ba317da318eca5ae19dcc0e4899c423e1 (patch) | |
tree | 81673c7e24181fbc77f360b9546b28a1a66ed7fe /test/format_test_vectors.py | |
parent | 9e564305d8941bceafc1b1c1d6d611b642c6dce9 (diff) |
Changes to the model:
* Follow what Verilog does more closely: FPGA can't do PP = P * P, because
it can't read from two different block mem P locations at the same time,
we have to do P1 = P2 = P, PP = P1 * P2
* Updated the test vector script to format additional quantities to help
debug Verilog exponentiation module
* Added the trick suggested by Bernd Paysan to help better conceal whether we're
discarding multiplication result when the current exponent bit is not set
Diffstat (limited to 'test/format_test_vectors.py')
-rw-r--r-- | test/format_test_vectors.py | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/test/format_test_vectors.py b/test/format_test_vectors.py index 21b9262..c56fe18 100644 --- a/test/format_test_vectors.py +++ b/test/format_test_vectors.py @@ -194,7 +194,7 @@ def calc_montgomery_n_coeff(k, n): # # format one test vector # -def format_verilog_include(f, key, n, m): +def format_verilog_include(f, key, n, m, d, s): # calculate factor to bring message into Montgomery domain factor = calc_montgomery_factor(int(key), n) @@ -215,6 +215,8 @@ def format_verilog_include(f, key, n, m): format_verilog_concatenation(f, factor, "localparam [" + str(int(key)-1) + ":0] FACTOR_" + str(key) + " =\n") format_verilog_concatenation(f, coeff, "localparam [" + str(int(key)-1) + ":0] COEFF_" + str(key) + " =\n") format_verilog_concatenation(f, m_factor, "localparam [" + str(int(key)-1) + ":0] M_FACTOR_" + str(key) + " =\n") + format_verilog_concatenation(f, d, "localparam [" + str(int(key)-1) + ":0] D_" + str(key) + " =\n") + format_verilog_concatenation(f, s, "localparam [" + str(int(key)-1) + ":0] S_" + str(key) + " =\n") # @@ -357,7 +359,7 @@ if __name__ == "__main__": # format numbers and write to file format_c_header(file_h, key, modulus, message, secret, signature, prime1, prime2, exponent1, exponent2, message1, message2) - format_verilog_include(file_v, key, modulus, message) + format_verilog_include(file_v, key, modulus, message, secret, signature) # done |