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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-18 02:14:27 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-07-18 02:14:27 +0300 |
| commit | 2db58a7ba317da318eca5ae19dcc0e4899c423e1 (patch) | |
| tree | 81673c7e24181fbc77f360b9546b28a1a66ed7fe /test/512.key | |
| parent | 9e564305d8941bceafc1b1c1d6d611b642c6dce9 (diff) | |
Changes to the model:
* Follow what Verilog does more closely: FPGA can't do PP = P * P, because
it can't read from two different block mem P locations at the same time,
we have to do P1 = P2 = P, PP = P1 * P2
* Updated the test vector script to format additional quantities to help
debug Verilog exponentiation module
* Added the trick suggested by Bernd Paysan to help better conceal whether we're
discarding multiplication result when the current exponent bit is not set
Diffstat (limited to 'test/512.key')
0 files changed, 0 insertions, 0 deletions