Changes to the model:

 * Follow what Verilog does more closely: FPGA can't do PP = P * P, because
   it can't read from two different block mem P locations at the same time,
   we have to do P1 = P2 = P, PP = P1 * P2
 * Updated the test vector script to format additional quantities to help
   debug Verilog exponentiation module
 * Added the trick suggested by Bernd Paysan to help better conceal whether we're
   discarding multiplication result when the current exponent bit is not set

0 files changed, 0 insertions, 0 deletions