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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-06-29 01:15:40 +0300 |
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| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2017-06-29 01:15:40 +0300 |
| commit | e91ce0765d40b3524f76f96c35aec6c85ded4c5f (patch) | |
| tree | 32a39699b85ea5ffd3c7ea918396457a78f5e688 /Makefile | |
| parent | 22f6cc0496f29d909c3f777d7c9b59559ab5723d (diff) | |
Follow what Verilog does more precisely.
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions