1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
|
//------------------------------------------------------------------------------
//
// fpga_lowlevel.cpp
// -----------------------------------
// Models of Low-level FPGA primitives
//
// Authors: Pavel Shatov
//
// Copyright (c) 2015-2016, NORDUnet A/S
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------
#include <stdint.h>
#include "ecdsa_model.h"
#include "fpga_lowlevel.h"
//------------------------------------------------------------------------------
//
// Low-level 32-bit adder with carry input and carry output.
//
// Carries are 1 bit wide.
//
// {c_out, s} = x + y + c_in
//
//------------------------------------------------------------------------------
void fpga_lowlevel_add32(FPGA_WORD x, FPGA_WORD y, bool c_in, FPGA_WORD *s, bool *c_out)
//------------------------------------------------------------------------------
{
// calculate sum
FPGA_WORD_EXTENDED r = (FPGA_WORD_EXTENDED)x + (FPGA_WORD_EXTENDED)y;
// process carry input
if (c_in) r++;
// store sum
*s = (FPGA_WORD)r;
// shift sum to obtain carry flag
r >>= FPGA_WORD_WIDTH;
// store carry
*c_out = (r != 0);
}
//------------------------------------------------------------------------------
//
// Low-level 32-bit subtractor with borrow input and borrow output.
//
// Borrows are 1 bit wide.
//
// {b_out, d} = x - y - b_in
//
void fpga_lowlevel_sub32(FPGA_WORD x, FPGA_WORD y, bool b_in, FPGA_WORD *d, bool *b_out)
//------------------------------------------------------------------------------
{
// calculate difference
FPGA_WORD_EXTENDED r = (FPGA_WORD_EXTENDED)x - (FPGA_WORD_EXTENDED)y;
// process borrow input
if (b_in) r--;
// store difference
*d = (FPGA_WORD)r;
// shift difference to obtain borrow flag
r >>= FPGA_WORD_WIDTH;
// store borrow
*b_out = (r != 0);
}
//------------------------------------------------------------------------------
//
// Low-level 16x16-bit multiplier.
//
// Inputs are 16-bit wide, outputs are 32-bit wide.
//
// p = x * y
//
void fpga_lowlevel_mul16(FPGA_WORD_REDUCED x, FPGA_WORD_REDUCED y, FPGA_WORD *p)
//------------------------------------------------------------------------------
{
// multiply and store result
*p = (FPGA_WORD)x * (FPGA_WORD)y;
}
//------------------------------------------------------------------------------
//
// Low-level 48-bit adder without carries.
//
// s = (x + y)[47:0]
//
void fpga_lowlevel_add48(FPGA_WORD_EXTENDED x, FPGA_WORD_EXTENDED y, FPGA_WORD_EXTENDED *s)
//------------------------------------------------------------------------------
{
// add and store result truncated to 48 bits
*s = (x + y) & FPGA_MASK_ADDER48;
}
//------------------------------------------------------------------------------
// End-of-File
//------------------------------------------------------------------------------
|
