| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | Makefile | 870 | logplainblame |
| -rw-r--r-- | README.md | 1308 | logplainblame |
| -rw-r--r-- | ecdsa_model.h | 9182 | logplainblame |
| -rw-r--r-- | ecdsa_model_fpga.cpp | 13565 | logplainblame |
| -rw-r--r-- | fpga_curve.cpp | 14077 | logplainblame |
| -rw-r--r-- | fpga_curve.h | 3100 | logplainblame |
| -rw-r--r-- | fpga_lowlevel.cpp | 4663 | logplainblame |
| -rw-r--r-- | fpga_lowlevel.h | 3704 | logplainblame |
| -rw-r--r-- | fpga_modular.cpp | 33863 | logplainblame |
| -rw-r--r-- | fpga_modular.h | 4090 | logplainblame |
| -rw-r--r-- | fpga_util.cpp | 3371 | logplainblame |
| -rw-r--r-- | fpga_util.h | 2317 | logplainblame |
 |
index : user/shatov/ecdsa_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
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