| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-12-19 | * New hardware architecture | Pavel V. Shatov (Meister) | |
| * Randomized test vector | |||
| 2017-02-06 | Minor cleanup | Pavel V. Shatov (Meister) | |
| * Fixed misplaced comma in 'ecdsa_model.h' * Rewrote P-384 reduction routine to match the style used in P-256 reduction | |||
| 2016-10-31 | Initial commit of FPGA base point multiplier reference model for ECDSA ↵ | Pavel V. Shatov (Meister) | |
| curves P-256 and P-384. | |||
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index : user/shatov/ecdsa_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
| aboutsummaryrefslogtreecommitdiff |
path: root/fpga_modular.cpp