| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-07-19 | Fixed copyright notices. | Pavel V. Shatov (Meister) | |
| 2021-04-12 | * cleaned up a bit | Pavel V. Shatov (Meister) | |
| * removed redundant check and refined microcode * re-enabled previously forgotten test | |||
| 2021-04-11 | Updated the top layer to accomodate changes in the underlying architecture. | Pavel V. Shatov (Meister) | |
| 2018-12-19 | * New hardware architecture | Pavel V. Shatov (Meister) | |
| * Randomized test vector | |||
 |
index : user/shatov/ecdsa_fpga_model | |
| Reference model written to help debug Verilog code | git repositories |
| aboutsummaryrefslogtreecommitdiff |
path: root/ecdsa_fpga_model.h