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| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2021-04-11 17:21:36 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2021-04-11 17:21:36 +0300 |
| commit | 516ca870fd3ad2a87e0ac56f0d453667e021c52d (patch) | |
| tree | de39313a891c387b1ee2f2cc6e7e892a4d263676 /ecdsa_fpga_model.h | |
| parent | 1b3b4b655b171e2e016970b19f0b43fdd2da5f8d (diff) | |
* Microcode layer redesigned to take advantage of Montgomery ladder
architecture. Instead of R and S there are now two working ("cycle") registers
R0 and R1. After every cycle R0+R1 is placed in register S ("sum"), 2*R0|1
(depending on current multiplier bit) is placed in register T. Then the working
variables are updated, final result ends up in R0.
* Due to the change of working registers, modular inversion routines were
updated accordingly.
* Added optional debugging output control
Diffstat (limited to 'ecdsa_fpga_model.h')
0 files changed, 0 insertions, 0 deletions