Age | Commit message (Expand) | Author |
---|---|---|
2020-09-23 | Finishing cleanup. Fixed schematics DRC errors (mostly missing NC flags on some | Pavel V. Shatov (Meister) |
2020-09-23 | Entirely routed the design. Not useable right now, so far just reports zero | Pavel V. Shatov (Meister) |
2020-09-23 | Intermediate step, re-routing the design according to the changes in schematics. | Pavel V. Shatov (Meister) |
2020-09-23 | Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA | Pavel V. Shatov (Meister) |
2020-09-23 | Turns out multi-part components were not fully converted and were not | Pavel V. Shatov (Meister) |
2020-04-23 | Copy of rev.04 project as-is after Fredrik's conversion script. | Pavel V. Shatov (Meister) |