diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:11:11 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:11:11 +0300 |
| commit | 1dee9e20eccc1cf3a6396d88c765b44faebacdd2 (patch) | |
| tree | 1189394c7bbb3bfd232397208b7c8bf5ac8bf108 /KiCAD/Cryptech Alpha.pro | |
| parent | a70ee229e036c7ae9ef61af5a73cc32ea6b773ca (diff) | |
Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA
along with it's power subsystem and programming circuitry.
Diffstat (limited to 'KiCAD/Cryptech Alpha.pro')
| -rw-r--r-- | KiCAD/Cryptech Alpha.pro | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/KiCAD/Cryptech Alpha.pro b/KiCAD/Cryptech Alpha.pro index 0068a54..8b8a44d 100644 --- a/KiCAD/Cryptech Alpha.pro +++ b/KiCAD/Cryptech Alpha.pro @@ -1,4 +1,4 @@ -update=21.06.2020 23:43:45 +update=06.07.2020 23:40:33 version=1 last_client=kicad [cvpcb] @@ -36,8 +36,12 @@ MinMicroViaDiameter=0.508 MinMicroViaDrill=0.127 MinHoleToHole=0.25 TrackWidth1=0.254 +TrackWidth2=0.15 +TrackWidth3=0.3 ViaDiameter1=0.889 ViaDrill1=0.25 +ViaDiameter2=0.5 +ViaDrill2=0.25 dPairWidth1=0.2 dPairGap1=0.25 dPairViaGap1=0.25 @@ -64,7 +68,7 @@ OthersTextUpright=1 SolderMaskClearance=0 SolderMaskMinWidth=0 SolderPasteClearance=0 -SolderPasteRatio=0 +SolderPasteRatio=-0 [pcbnew/Layer.F.Cu] Name=F.Cu Type=0 |