user/shatov/alpha_rev04 - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author
2020-09-23	Doing some final polishing, added the "Open Source Hardware" logo I removed	Pavel V. Shatov (Meister)
2020-09-23	Finished cleanup, fixed all pcbnew DRC errors reported. First attempt at	Pavel V. Shatov (Meister)
2020-09-23	Did some cleanup, also had to re-route VCC_PLL for iCE40.	Pavel V. Shatov (Meister)
2020-09-23	Entirely routed the design. Not useable right now, so far just reports zero	Pavel V. Shatov (Meister)
2020-09-23	Intermediate step, re-routing the design according to the changes in schematics.	Pavel V. Shatov (Meister)
2020-09-23	Almost finished doing edits to schematics. Added Lattice iCE40 UltraPlus FPGA	Pavel V. Shatov (Meister)
2020-09-23	Continued doing edits. Removed AVR tiny tamper detection processor.	Pavel V. Shatov (Meister)
2020-09-23	Started editing the design. So far removed the old MKM component.	Pavel V. Shatov (Meister)
2020-09-23	Forward annotation (eeschema -> pcbnew) is now FULLY OPERATIONAL! Hoorah!	Pavel V. Shatov (Meister)
2020-09-23	Turns out multi-part components were not fully converted and were not	Pavel V. Shatov (Meister)
2020-09-23	Fixed PCB footprint references. Basically had to just replace dashes with	Pavel V. Shatov (Meister)
2020-09-23	Initial project cleanup	Pavel V. Shatov (Meister)
2020-05-25	Internal ground layers OK.	Pavel V. Shatov (Meister)
2020-05-25	Bottom Layer OK	Pavel V. Shatov (Meister)
2020-05-25	Internal signal layer #2 cleaned up.	Pavel V. Shatov (Meister)
2020-05-25	Internal signal layer #1 cleaned up.	Pavel V. Shatov (Meister)
2020-05-11	Top (aka "Front") Layer OK	Pavel V. Shatov (Meister)
2020-04-23	Copy of rev.04 project as-is after Fredrik's conversion script.	Pavel V. Shatov (Meister)