diff options
Diffstat (limited to 'KiCAD/Cryptech Alpha.kicad_pcb')
| -rw-r--r-- | KiCAD/Cryptech Alpha.kicad_pcb | 30530 |
1 files changed, 30530 insertions, 0 deletions
diff --git a/KiCAD/Cryptech Alpha.kicad_pcb b/KiCAD/Cryptech Alpha.kicad_pcb new file mode 100644 index 0000000..a57e734 --- /dev/null +++ b/KiCAD/Cryptech Alpha.kicad_pcb @@ -0,0 +1,30530 @@ +(kicad_pcb (version 20171130) (host pcbnew "(5.1.5)-3") + + (general + (thickness 1.6) + (drawings 6691) + (tracks 9160) + (zones 0) + (modules 386) + (nets 304) + ) + + (page A4) + (layers + (0 F.Cu signal hide) + (1 In1.Cu power hide) + (2 In2.Cu mixed hide) + (3 In3.Cu power hide) + (4 In4.Cu power hide) + (5 In5.Cu mixed hide) + (6 In6.Cu power hide) + (31 B.Cu signal hide) + (32 B.Adhes user hide) + (33 F.Adhes user hide) + (34 B.Paste user hide) + (35 F.Paste user hide) + (36 B.SilkS user hide) + (37 F.SilkS user hide) + (38 B.Mask user hide) + (39 F.Mask user hide) + (40 Dwgs.User user hide) + (41 Cmts.User user hide) + (42 Eco1.User user hide) + (43 Eco2.User user hide) + (44 Edge.Cuts user hide) + (45 Margin user hide) + (46 B.CrtYd user hide) + (47 F.CrtYd user hide) + (48 B.Fab user hide) + (49 F.Fab user hide) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.125) + (zone_clearance 0.0144) + (zone_45_only no) + (trace_min 0.15) + (via_size 0.889) + (via_drill 0.25) + (via_min_size 0.5) + (via_min_drill 0.25) + (uvia_size 0.508) + (uvia_drill 0.127) + (uvias_allowed no) + (uvia_min_size 0.508) + (uvia_min_drill 0.127) + (edge_width 0.1) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.5 1.5) + (pad_drill 0.6) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements 7FFED33F) + (pcbplotparams + (layerselection 0x01000_7fffff80) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "C:/Users/Paul/YandexDisk/DEV/CrypTech/git/user/shatov/alpha_rev04/NewGerbers/")) + ) + + (net 0 "") + (net 1 Net1) + (net 2 DM_P) + (net 3 DM_N) + (net 4 3V3_BATT) + (net 5 15V_LDO_ENABLE) + (net 6 15V_STABLE) + (net 7 GND) + (net 8 "Net-(C15-Pad2)") + (net 9 AMPLIFIED) + (net 10 ARM_FPGA_CFG_CS_N) + (net 11 ARM_FPGA_CFG_MISO) + (net 12 ARM_FPGA_CFG_MOSI) + (net 13 ARM_FPGA_CFG_SCLK) + (net 14 ARM_LED1) + (net 15 ARM_LED2) + (net 16 ARM_LED3) + (net 17 ARM_LED4) + (net 18 AVR_GPIO_0) + (net 19 AVR_GPIO_1) + (net 20 AVR_GPIO_2) + (net 21 AVR_GPIO_3) + (net 22 AVR_GPIO_4) + (net 23 AVR_GPIO_5) + (net 24 AVR_GPIO_6) + (net 25 AVR_GPIO_7) + (net 26 AVR_GPIO_ARM_0) + (net 27 AVR_GPIO_ARM_1) + (net 28 AVR_GPIO_ARM_2) + (net 29 AVR_GPIO_ARM_3) + (net 30 AVR_GPIO_FPGA_0) + (net 31 AVR_GPIO_FPGA_1) + (net 32 AVR_GPIO_FPGA_2) + (net 33 AVR_GPIO_FPGA_3) + (net 34 AVR_LED1) + (net 35 AVR_LED2) + (net 36 AVR_LED3) + (net 37 AVR_LED4) + (net 38 AVR_PANIC) + (net 39 AVR_RESET) + (net 40 BOOT0) + (net 41 D1_N) + (net 42 D1_P) + (net 43 DIGITIZED_NOISE) + (net 44 FMC_A0) + (net 45 FMC_A1) + (net 46 FMC_A2) + (net 47 FMC_A3) + (net 48 FMC_A4) + (net 49 FMC_A5) + (net 50 FMC_A6) + (net 51 FMC_A7) + (net 52 FMC_A8) + (net 53 FMC_A9) + (net 54 FMC_A10) + (net 55 FMC_A11) + (net 56 FMC_A12) + (net 57 FMC_A13) + (net 58 FMC_A14) + (net 59 FMC_A15) + (net 60 FMC_A16) + (net 61 FMC_A17) + (net 62 FMC_A18) + (net 63 FMC_A19) + (net 64 FMC_A20) + (net 65 FMC_A21) + (net 66 FMC_A22) + (net 67 FMC_A23) + (net 68 FMC_A24) + (net 69 FMC_A25) + (net 70 FMC_CLK) + (net 71 FMC_D0) + (net 72 FMC_D1) + (net 73 FMC_D2) + (net 74 FMC_D3) + (net 75 FMC_D4) + (net 76 FMC_D5) + (net 77 FMC_D6) + (net 78 FMC_D7) + (net 79 FMC_D8) + (net 80 FMC_D9) + (net 81 FMC_D10) + (net 82 FMC_D11) + (net 83 FMC_D12) + (net 84 FMC_D13) + (net 85 FMC_D14) + (net 86 FMC_D15) + (net 87 FMC_D16) + (net 88 FMC_D17) + (net 89 FMC_D18) + (net 90 FMC_D19) + (net 91 FMC_D20) + (net 92 FMC_D21) + (net 93 FMC_D22) + (net 94 FMC_D23) + (net 95 FMC_D24) + (net 96 FMC_D25) + (net 97 FMC_D26) + (net 98 FMC_D27) + (net 99 FMC_D28) + (net 100 FMC_D29) + (net 101 FMC_D30) + (net 102 FMC_D31) + (net 103 FMC_NBL0) + (net 104 FMC_NBL1) + (net 105 FMC_NBL2) + (net 106 FMC_NBL3) + (net 107 FMC_NE1) + (net 108 FMC_NL) + (net 109 FMC_NOE) + (net 110 FMC_NWAIT) + (net 111 FMC_NWE) + (net 112 FMC_SDCKE0) + (net 113 FMC_SDCKE1) + (net 114 FMC_SDCLK) + (net 115 FMC_SDNCAS) + (net 116 FMC_SDNE0) + (net 117 FMC_SDNE1) + (net 118 FMC_SDNRAS) + (net 119 FMC_SDNWE) + (net 120 FPGA_CFG_CS_N1) + (net 121 FPGA_CFG_CS_N) + (net 122 FPGA_CFG_CTRL_ARM_ENA) + (net 123 FPGA_CFG_CTRL_FPGA_DIS) + (net 124 FPGA_CFG_MISO1) + (net 125 FPGA_CFG_MISO) + (net 126 FPGA_CFG_MOSI1) + (net 127 FPGA_CFG_MOSI) + (net 128 FPGA_CFG_SCLK1) + (net 129 FPGA_CFG_SCLK) + (net 130 FPGA_DONE_INT) + (net 131 FPGA_DONE) + (net 132 FPGA_ENTROPY_DISABLE) + (net 133 FPGA_GCLK) + (net 134 FPGA_GPIO_A_0) + (net 135 FPGA_GPIO_A_1) + (net 136 FPGA_GPIO_A_2) + (net 137 FPGA_GPIO_A_3) + (net 138 FPGA_GPIO_A_4) + (net 139 FPGA_GPIO_A_5) + (net 140 FPGA_GPIO_A_6) + (net 141 FPGA_GPIO_A_7) + (net 142 FPGA_GPIO_B_0) + (net 143 FPGA_GPIO_B_1) + (net 144 FPGA_GPIO_B_2) + (net 145 FPGA_GPIO_B_3) + (net 146 FPGA_GPIO_B_4) + (net 147 FPGA_GPIO_B_5) + (net 148 FPGA_GPIO_B_6) + (net 149 FPGA_GPIO_B_7) + (net 150 FPGA_GPIO_LED_0) + (net 151 FPGA_GPIO_LED_1) + (net 152 FPGA_GPIO_LED_2) + (net 153 FPGA_GPIO_LED_3) + (net 154 FPGA_INIT_B_INT1) + (net 155 FPGA_INIT_B_INT) + (net 156 FPGA_INIT_B) + (net 157 FPGA_IRQ_N_0) + (net 158 FPGA_IRQ_N_1) + (net 159 FPGA_IRQ_N_2) + (net 160 FPGA_IRQ_N_3) + (net 161 FPGA_JTAG_TCK) + (net 162 FPGA_JTAG_TDI) + (net 163 FPGA_JTAG_TDO) + (net 164 FPGA_JTAG_TMS) + (net 165 FPGA_M0) + (net 166 FPGA_M1) + (net 167 FPGA_M2) + (net 168 FPGA_PROGRAM_B1) + (net 169 FPGA_PROGRAM_B) + (net 170 FPGA_PROM_CS_N) + (net 171 FPGA_PROM_MISO) + (net 172 FPGA_PROM_MOSI) + (net 173 FPGA_PROM_SCLK) + (net 174 FPGA_PROM_W_N) + (net 175 FPGA_VCCAUX_1V8) + (net 176 FPGA_VCCINT_1V0) + (net 177 FT_CTS) + (net 178 FT_DTR) + (net 179 FT_MGMT_CTS) + (net 180 FT_MGMT_DTR) + (net 181 FT_MGMT_RTS) + (net 182 FT_MGMT_RXD1) + (net 183 FT_MGMT_RXD) + (net 184 FT_MGMT_TXD1) + (net 185 FT_MGMT_TXD) + (net 186 FT_MGMT_VCC3V3) + (net 187 FT_MGMT_VPHY) + (net 188 FT_MGMT_VPLL) + (net 189 FT_MGMT_VREGIN) + (net 190 FT_REF1) + (net 191 FT_REF) + (net 192 FT_RESET1) + (net 193 FT_RESET) + (net 194 FT_RTS) + (net 195 FT_RXD1) + (net 196 FT_RXD) + (net 197 FT_TXD1) + (net 198 FT_TXD) + (net 199 FT_VCC3V3) + (net 200 FT_VCCA1) + (net 201 FT_VCCA) + (net 202 FT_VCCORE1) + (net 203 FT_VCCORE) + (net 204 FT_VPHY) + (net 205 FT_VPLL) + (net 206 FT_VREGIN) + (net 207 KSM_PROM_CS_N) + (net 208 KSM_PROM_MISO) + (net 209 KSM_PROM_MOSI) + (net 210 KSM_PROM_SCLK) + (net 211 MKM_AVR_CS_N) + (net 212 MKM_AVR_MISO) + (net 213 MKM_AVR_MOSI) + (net 214 MKM_AVR_SCK) + (net 215 MKM_CONTROL_AVR_ENA) + (net 216 MKM_CONTROL_FPGA_DIS) + (net 217 MKM_CS_N) + (net 218 MKM_FPGA_CS_N) + (net 219 MKM_FPGA_MISO) + (net 220 MKM_FPGA_MOSI) + (net 221 MKM_FPGA_SCK) + (net 222 MKM_MISO) + (net 223 MKM_MOSI) + (net 224 MKM_SCK) + (net 225 "Net-(C5-Pad1)") + (net 226 "Net-(C11-Pad1)") + (net 227 "Net-(C12-Pad2)") + (net 228 "Net-(C17-Pad2)") + (net 229 "Net-(C70-Pad2)") + (net 230 "Net-(C71-Pad2)") + (net 231 "Net-(C75-Pad2)") + (net 232 "Net-(C78-Pad2)") + (net 233 "Net-(C90-Pad2)") + (net 234 "Net-(C93-Pad2)") + (net 235 "Net-(C115-Pad1)") + (net 236 "Net-(C116-Pad1)") + (net 237 "Net-(C117-Pad1)") + (net 238 "Net-(C117-Pad2)") + (net 239 "Net-(C118-Pad1)") + (net 240 "Net-(C118-Pad2)") + (net 241 "Net-(C207-Pad1)") + (net 242 "Net-(C208-Pad1)") + (net 243 "Net-(C208-Pad2)") + (net 244 "Net-(IC1-Pad3)") + (net 245 "Net-(JP2-Pad2)") + (net 246 "Net-(LED1-Pad1)") + (net 247 "Net-(LED2-Pad1)") + (net 248 "Net-(LED3-Pad1)") + (net 249 "Net-(LED4-Pad1)") + (net 250 "Net-(LED9-Pad1)") + (net 251 "Net-(LED10-Pad1)") + (net 252 "Net-(LED11-Pad1)") + (net 253 "Net-(LED12-Pad1)") + (net 254 "Net-(LED13-Pad1)") + (net 255 "Net-(LED14-Pad1)") + (net 256 "Net-(LED15-Pad1)") + (net 257 "Net-(LED16-Pad1)") + (net 258 "Net-(LED17-Pad1)") + (net 259 "Net-(LED18-Pad1)") + (net 260 "Net-(LED18-Pad2)") + (net 261 "Net-(Q1-Pad1)") + (net 262 "Net-(Q5-Pad1)") + (net 263 "Net-(Q5-Pad3)") + (net 264 "Net-(R1-Pad1)") + (net 265 "Net-(R3-Pad2)") + (net 266 "Net-(R8-Pad1)") + (net 267 "Net-(R32-Pad2)") + (net 268 "Net-(R33-Pad2)") + (net 269 "Net-(R52-Pad1)") + (net 270 "Net-(R53-Pad2)") + (net 271 "Net-(R54-Pad1)") + (net 272 "Net-(R55-Pad2)") + (net 273 "Net-(R65-Pad1)") + (net 274 "Net-(R66-Pad1)") + (net 275 "Net-(R67-Pad1)") + (net 276 NOISE_IN) + (net 277 NOISE_OUT) + (net 278 NRST) + (net 279 OSC_IN) + (net 280 OSC_OUT) + (net 281 POK_VCCAUX) + (net 282 POK_VCCINT) + (net 283 POK_VCCO) + (net 284 PWR_18V) + (net 285 PWR_ENA_VCCAUX) + (net 286 PWR_ENA_VCCINT) + (net 287 PWR_ENA_VCCO) + (net 288 RAW_NOISE) + (net 289 RTC_MFP) + (net 290 RTC_SCL) + (net 291 RTC_SDA) + (net 292 SPI_A_TRISTATE) + (net 293 SPI_B_TRISTATE) + (net 294 SWDCLK) + (net 295 SWDIO) + (net 296 USB_MGMT_N) + (net 297 USB_MGMT_P) + (net 298 USB_N) + (net 299 USB_P) + (net 300 VCAP1) + (net 301 VCAP2) + (net 302 VCC_5V0) + (net 303 VCCO_3V3) + + (net_class Default "This is the default net class." + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net 15V_LDO_ENABLE) + (add_net 15V_STABLE) + (add_net 3V3_BATT) + (add_net AMPLIFIED) + (add_net ARM_FPGA_CFG_CS_N) + (add_net ARM_FPGA_CFG_MISO) + (add_net ARM_FPGA_CFG_MOSI) + (add_net ARM_FPGA_CFG_SCLK) + (add_net ARM_LED1) + (add_net ARM_LED2) + (add_net ARM_LED3) + (add_net ARM_LED4) + (add_net AVR_GPIO_0) + (add_net AVR_GPIO_1) + (add_net AVR_GPIO_2) + (add_net AVR_GPIO_3) + (add_net AVR_GPIO_4) + (add_net AVR_GPIO_5) + (add_net AVR_GPIO_6) + (add_net AVR_GPIO_7) + (add_net AVR_GPIO_ARM_0) + (add_net AVR_GPIO_ARM_1) + (add_net AVR_GPIO_ARM_2) + (add_net AVR_GPIO_ARM_3) + (add_net AVR_GPIO_FPGA_0) + (add_net AVR_GPIO_FPGA_1) + (add_net AVR_GPIO_FPGA_2) + (add_net AVR_GPIO_FPGA_3) + (add_net AVR_LED1) + (add_net AVR_LED2) + (add_net AVR_LED3) + (add_net AVR_LED4) + (add_net AVR_PANIC) + (add_net AVR_RESET) + (add_net BOOT0) + (add_net DIGITIZED_NOISE) + (add_net FPGA_CFG_CS_N) + (add_net FPGA_CFG_CS_N1) + (add_net FPGA_CFG_CTRL_ARM_ENA) + (add_net FPGA_CFG_CTRL_FPGA_DIS) + (add_net FPGA_CFG_MISO) + (add_net FPGA_CFG_MISO1) + (add_net FPGA_CFG_MOSI) + (add_net FPGA_CFG_MOSI1) + (add_net FPGA_CFG_SCLK) + (add_net FPGA_CFG_SCLK1) + (add_net FPGA_DONE) + (add_net FPGA_DONE_INT) + (add_net FPGA_ENTROPY_DISABLE) + (add_net FPGA_GCLK) + (add_net FPGA_GPIO_LED_0) + (add_net FPGA_GPIO_LED_1) + (add_net FPGA_GPIO_LED_2) + (add_net FPGA_GPIO_LED_3) + (add_net FPGA_INIT_B) + (add_net FPGA_INIT_B_INT) + (add_net FPGA_INIT_B_INT1) + (add_net FPGA_IRQ_N_0) + (add_net FPGA_IRQ_N_1) + (add_net FPGA_IRQ_N_2) + (add_net FPGA_IRQ_N_3) + (add_net FPGA_JTAG_TCK) + (add_net FPGA_JTAG_TDI) + (add_net FPGA_JTAG_TDO) + (add_net FPGA_JTAG_TMS) + (add_net FPGA_M0) + (add_net FPGA_M1) + (add_net FPGA_M2) + (add_net FPGA_PROGRAM_B) + (add_net FPGA_PROGRAM_B1) + (add_net FPGA_PROM_CS_N) + (add_net FPGA_PROM_MISO) + (add_net FPGA_PROM_MOSI) + (add_net FPGA_PROM_SCLK) + (add_net FPGA_PROM_W_N) + (add_net FPGA_VCCAUX_1V8) + (add_net FPGA_VCCINT_1V0) + (add_net FT_CTS) + (add_net FT_DTR) + (add_net FT_MGMT_CTS) + (add_net FT_MGMT_DTR) + (add_net FT_MGMT_RTS) + (add_net FT_MGMT_RXD) + (add_net FT_MGMT_RXD1) + (add_net FT_MGMT_TXD) + (add_net FT_MGMT_TXD1) + (add_net FT_MGMT_VCC3V3) + (add_net FT_MGMT_VPHY) + (add_net FT_MGMT_VPLL) + (add_net FT_MGMT_VREGIN) + (add_net FT_REF) + (add_net FT_REF1) + (add_net FT_RESET) + (add_net FT_RESET1) + (add_net FT_RTS) + (add_net FT_RXD) + (add_net FT_RXD1) + (add_net FT_TXD) + (add_net FT_TXD1) + (add_net FT_VCC3V3) + (add_net FT_VCCA) + (add_net FT_VCCA1) + (add_net FT_VCCORE) + (add_net FT_VCCORE1) + (add_net FT_VPHY) + (add_net FT_VPLL) + (add_net FT_VREGIN) + (add_net GND) + (add_net KSM_PROM_CS_N) + (add_net KSM_PROM_MISO) + (add_net KSM_PROM_MOSI) + (add_net KSM_PROM_SCLK) + (add_net MKM_AVR_CS_N) + (add_net MKM_AVR_MISO) + (add_net MKM_AVR_MOSI) + (add_net MKM_AVR_SCK) + (add_net MKM_CONTROL_AVR_ENA) + (add_net MKM_CONTROL_FPGA_DIS) + (add_net MKM_CS_N) + (add_net MKM_FPGA_CS_N) + (add_net MKM_FPGA_MISO) + (add_net MKM_FPGA_MOSI) + (add_net MKM_FPGA_SCK) + (add_net MKM_MISO) + (add_net MKM_MOSI) + (add_net MKM_SCK) + (add_net NOISE_IN) + (add_net NOISE_OUT) + (add_net NRST) + (add_net "Net-(C11-Pad1)") + (add_net "Net-(C115-Pad1)") + (add_net "Net-(C116-Pad1)") + (add_net "Net-(C117-Pad1)") + (add_net "Net-(C117-Pad2)") + (add_net "Net-(C118-Pad1)") + (add_net "Net-(C118-Pad2)") + (add_net "Net-(C12-Pad2)") + (add_net "Net-(C15-Pad2)") + (add_net "Net-(C17-Pad2)") + (add_net "Net-(C207-Pad1)") + (add_net "Net-(C208-Pad1)") + (add_net "Net-(C208-Pad2)") + (add_net "Net-(C5-Pad1)") + (add_net "Net-(C70-Pad2)") + (add_net "Net-(C71-Pad2)") + (add_net "Net-(C75-Pad2)") + (add_net "Net-(C78-Pad2)") + (add_net "Net-(C90-Pad2)") + (add_net "Net-(C93-Pad2)") + (add_net "Net-(IC1-Pad3)") + (add_net "Net-(JP2-Pad2)") + (add_net "Net-(LED1-Pad1)") + (add_net "Net-(LED10-Pad1)") + (add_net "Net-(LED11-Pad1)") + (add_net "Net-(LED12-Pad1)") + (add_net "Net-(LED13-Pad1)") + (add_net "Net-(LED14-Pad1)") + (add_net "Net-(LED15-Pad1)") + (add_net "Net-(LED16-Pad1)") + (add_net "Net-(LED17-Pad1)") + (add_net "Net-(LED18-Pad1)") + (add_net "Net-(LED18-Pad2)") + (add_net "Net-(LED2-Pad1)") + (add_net "Net-(LED3-Pad1)") + (add_net "Net-(LED4-Pad1)") + (add_net "Net-(LED9-Pad1)") + (add_net "Net-(Q1-Pad1)") + (add_net "Net-(Q5-Pad1)") + (add_net "Net-(Q5-Pad3)") + (add_net "Net-(R1-Pad1)") + (add_net "Net-(R3-Pad2)") + (add_net "Net-(R32-Pad2)") + (add_net "Net-(R33-Pad2)") + (add_net "Net-(R52-Pad1)") + (add_net "Net-(R53-Pad2)") + (add_net "Net-(R54-Pad1)") + (add_net "Net-(R55-Pad2)") + (add_net "Net-(R65-Pad1)") + (add_net "Net-(R66-Pad1)") + (add_net "Net-(R67-Pad1)") + (add_net "Net-(R8-Pad1)") + (add_net Net1) + (add_net OSC_IN) + (add_net OSC_OUT) + (add_net POK_VCCAUX) + (add_net POK_VCCINT) + (add_net POK_VCCO) + (add_net PWR_18V) + (add_net PWR_ENA_VCCAUX) + (add_net PWR_ENA_VCCINT) + (add_net PWR_ENA_VCCO) + (add_net RAW_NOISE) + (add_net RTC_MFP) + (add_net RTC_SCL) + (add_net RTC_SDA) + (add_net SPI_A_TRISTATE) + (add_net SPI_B_TRISTATE) + (add_net SWDCLK) + (add_net SWDIO) + (add_net VCAP1) + (add_net VCAP2) + (add_net VCCO_3V3) + (add_net VCC_5V0) + ) + + (net_class FMC FMC + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net FMC_A0) + (add_net FMC_A1) + (add_net FMC_A10) + (add_net FMC_A11) + (add_net FMC_A12) + (add_net FMC_A13) + (add_net FMC_A14) + (add_net FMC_A15) + (add_net FMC_A16) + (add_net FMC_A17) + (add_net FMC_A18) + (add_net FMC_A19) + (add_net FMC_A2) + (add_net FMC_A20) + (add_net FMC_A21) + (add_net FMC_A22) + (add_net FMC_A23) + (add_net FMC_A24) + (add_net FMC_A25) + (add_net FMC_A3) + (add_net FMC_A4) + (add_net FMC_A5) + (add_net FMC_A6) + (add_net FMC_A7) + (add_net FMC_A8) + (add_net FMC_A9) + (add_net FMC_CLK) + (add_net FMC_D0) + (add_net FMC_D1) + (add_net FMC_D10) + (add_net FMC_D11) + (add_net FMC_D12) + (add_net FMC_D13) + (add_net FMC_D14) + (add_net FMC_D15) + (add_net FMC_D16) + (add_net FMC_D17) + (add_net FMC_D18) + (add_net FMC_D19) + (add_net FMC_D2) + (add_net FMC_D20) + (add_net FMC_D21) + (add_net FMC_D22) + (add_net FMC_D23) + (add_net FMC_D24) + (add_net FMC_D25) + (add_net FMC_D26) + (add_net FMC_D27) + (add_net FMC_D28) + (add_net FMC_D29) + (add_net FMC_D3) + (add_net FMC_D30) + (add_net FMC_D31) + (add_net FMC_D4) + (add_net FMC_D5) + (add_net FMC_D6) + (add_net FMC_D7) + (add_net FMC_D8) + (add_net FMC_D9) + (add_net FMC_NBL0) + (add_net FMC_NBL1) + (add_net FMC_NBL2) + (add_net FMC_NBL3) + (add_net FMC_NE1) + (add_net FMC_NL) + (add_net FMC_NOE) + (add_net FMC_NWAIT) + (add_net FMC_NWE) + (add_net FMC_SDCKE0) + (add_net FMC_SDCKE1) + (add_net FMC_SDCLK) + (add_net FMC_SDNCAS) + (add_net FMC_SDNE0) + (add_net FMC_SDNE1) + (add_net FMC_SDNRAS) + (add_net FMC_SDNWE) + ) + + (net_class FPGA_GPIO FPGA_GPIO + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net FPGA_GPIO_A_0) + (add_net FPGA_GPIO_A_1) + (add_net FPGA_GPIO_A_2) + (add_net FPGA_GPIO_A_3) + (add_net FPGA_GPIO_A_4) + (add_net FPGA_GPIO_A_5) + (add_net FPGA_GPIO_A_6) + (add_net FPGA_GPIO_A_7) + (add_net FPGA_GPIO_B_0) + (add_net FPGA_GPIO_B_1) + (add_net FPGA_GPIO_B_2) + (add_net FPGA_GPIO_B_3) + (add_net FPGA_GPIO_B_4) + (add_net FPGA_GPIO_B_5) + (add_net FPGA_GPIO_B_6) + (add_net FPGA_GPIO_B_7) + ) + + (net_class USB USB + (clearance 0.125) + (trace_width 0.254) + (via_dia 0.889) + (via_drill 0.25) + (uvia_dia 0.508) + (uvia_drill 0.127) + (add_net D1_N) + (add_net D1_P) + (add_net DM_N) + (add_net DM_P) + (add_net USB_MGMT_N) + (add_net USB_MGMT_P) + (add_net USB_N) + (add_net USB_P) + ) + + (module Cryptech_Alpha_Footprints:_HDR1X10_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 31.5 6) + (path /539EEC0F) + (attr smd) + (fp_text reference JP5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 10-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115)." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole circle (at 5.08 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 19 AVR_GPIO_1)) + (pad 10 thru_hole circle (at 22.86 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 9 thru_hole circle (at 20.32 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 25 AVR_GPIO_7)) + (pad 8 thru_hole circle (at 17.78 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 24 AVR_GPIO_6)) + (pad 7 thru_hole circle (at 15.24 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 23 AVR_GPIO_5)) + (pad 6 thru_hole circle (at 12.7 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 22 AVR_GPIO_4)) + (pad 5 thru_hole circle (at 10.16 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 21 AVR_GPIO_3)) + (pad 4 thru_hole circle (at 7.62 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 20 AVR_GPIO_2)) + (pad 2 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 18 AVR_GPIO_0)) + (pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-2_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 84.16075 -31.8) + (path /539EEC0F) + (attr smd) + (fp_text reference JP6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -0.00001 1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -0.00001 -1.27 90) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 212 MKM_AVR_MISO)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz -11.80693582267761 5.675121914768218 -6.799998997874261)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/3416A7AC-A52A.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 21.463 -99.0854) + (path /539EEC0F) + (attr smd) + (fp_text reference C1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 21.463 -94.0689) + (path /539EEC0F) + (attr smd) + (fp_text reference C2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 21.463 -89.0524) + (path /539EEC0F) + (attr smd) + (fp_text reference C3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 26.1 -84.7) + (path /539EEC0F) + (attr smd) + (fp_text reference C4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.55 -75.725) + (path /539EEC0F) + (attr smd) + (fp_text reference C5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 225 "Net-(C5-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.5778 -71.8312) + (path /539EEC0F) + (attr smd) + (fp_text reference C6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0805_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 72.5 -86.5) + (path /539EEC0F) + (attr smd) + (fp_text reference C7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0805 CAPACITOR X7R 25V" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at -1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1 0 180) (size 1 1.2) (layers F.Cu F.Paste F.Mask) + (net 284 PWR_18V)) + (model "wrlshp/SW3dPS-0805 SMD Capacitor.wrl" + (offset (xyz 0 0.02489199962615967 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/68E8DA21-73BF.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 15.2908 -67.3354) + (path /539EEC0F) + (attr smd) + (fp_text reference C8 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR X5R 6.3V" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 1.5 0 180) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 2 smd rect (at -1.5 0 180) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 -1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_D_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 10.4648 -54.5846) + (path /539EEC0F) + (attr smd) + (fp_text reference C9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Kemet Tantalum Capacitor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-cap_d.wrl + (offset (xyz -0.05003799924850464 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/5917D381-109F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_D_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 10.4648 -61.0616) + (path /539EEC0F) + (attr smd) + (fp_text reference C10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Kemet Tantalum Capacitor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at -3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 3.25 0 180) (size 2.4 2.6) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (model wrlshp/SW3dPS-cap_d.wrl + (offset (xyz -0.05003799924850464 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/5917D381-109F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74.5 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(thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 227 "Net-(C12-Pad2)")) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0805_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 76.25 -87.75) + (path /539EEC0F) + (attr smd) + (fp_text reference C13 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0805 CAPACITOR X7R 25V" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) 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smd) + (fp_text reference C205 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "1210 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 2 smd rect (at 1.5 0) (size 1.6 2.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-CAPC3225.wrl + (offset (xyz 0 1.249933981227875 1.250000021226883)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_1210_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 22.0472 -46.2788) + (path /539EEC0F) + (attr smd) + (fp_text reference C206 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text 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360 90)) + ) + (model wrlshp/F26EE9BE-B6B0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 24.003 -63.0936) + (path /539EEC0F) + (attr smd) + (fp_text reference C211 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 286 PWR_ENA_VCCINT)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 14.8336 -47.2694) + (path /539EEC0F) + (attr smd) + (fp_text reference C212 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 CAPACITOR" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 287 PWR_ENA_VCCO)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_C_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 30.9118 -76.327) + (path /539EEC0F) + (attr smd) + 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F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Capacitor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/ECAF1ED8-FCC0.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_USB-MINIB_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 65 14.9) + (path /539EEC0F) + (attr smd) + (fp_text reference CN1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "mini USB type B Connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 42 D1_P)) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 41 D1_N)) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/c-1734035-2-e-3d.wrl + (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/23D50C2B-5C98.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_USB-MINIB_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 85 14.9) + (path /539EEC0F) + (attr smd) + (fp_text reference CN2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "mini USB type B Connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad "" np_thru_hole circle (at -2.2 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad "" np_thru_hole circle (at 2.2098 -1.016) (size 1.016 1.016) (drill 1.1) (layers *.Cu *.Paste *.Mask)) + (pad GND smd rect (at -4.34 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad VBUS smd rect (at -1.6 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad D- smd rect (at -0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 3 DM_N)) + (pad D+ smd rect (at 0 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 2 DM_P)) + (pad ID smd rect (at 0.8 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask)) + (pad GND smd rect (at 1.6002 -3.7 180) (size 0.6 1.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at -4.34 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 4.36 -3.5052) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad GND smd rect (at 4.36 2) (size 1.6 2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/c-1734035-2-e-3d.wrl + (offset (xyz 0.02539999961853028 -5.009133924770355 2.000001049962997)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/23D50C2B-5C98.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.8548 -89.1794) + (path /539EEC0F) + (attr smd) + (fp_text reference D1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi Schottky Diode" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (pad 2 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask)) + (pad 1 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 8 "Net-(C15-Pad2)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 20.9804 -63.5508) + (path /539EEC0F) + (attr smd) + (fp_text reference D2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi Schottky Diode" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 286 PWR_ENA_VCCINT)) + (pad 2 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 302 VCC_5V0)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 11.6078 -47.2694) + (path /539EEC0F) + (attr smd) + (fp_text reference D3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi Schottky Diode" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 281 POK_VCCAUX)) + (pad 2 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 287 PWR_ENA_VCCO)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 32.8168 -72.9234) + (path /539EEC0F) + (attr smd) + (fp_text reference D4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi Schottky Diode" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 285 PWR_ENA_VCCAUX)) + (pad 2 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 282 POK_VCCINT)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 27.3512 -15.7226) + (path /539EEC0F) + (attr smd) + (fp_text reference FB1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 204 FT_VPHY)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 20.7528 -14.9192) + (path /539EEC0F) + (attr smd) + (fp_text reference FB2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.85 0 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 205 FT_VPLL)) + (pad 1 smd rect (at -0.85 0 90) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 0)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 93.218 -10.9662) + (path /539EEC0F) + (attr smd) + (fp_text reference FB3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 187 FT_MGMT_VPHY)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 91.186 -10.9662) + (path /539EEC0F) + (attr smd) + (fp_text reference FB4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Ferrite Bead 600 Ohm 500mA" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 188 FT_MGMT_VPLL)) + (pad 1 smd rect (at 0 -0.85) (size 1 0.9) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (model "wrlshp/User Library-V0603HD.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 90)) + ) + (model wrlshp/AF13F747-700F.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.4528 -84.2772) + (path /539EEC0F) + (attr smd) + (fp_text reference FB5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad 1 smd rect (at -1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 7.7978 -33.147) + (path /539EEC0F) + (attr smd) + (fp_text reference FB6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 2 smd rect (at 1.4 0 270) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_L_1206_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.624 -58.2168) + (path /539EEC0F) + (attr smd) + (fp_text reference FB7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad 1 smd rect (at 0 1.4) (size 1.8 1.4) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (model "wrlshp/User Library-V1206HD.wrl" + (offset (xyz 0.05003799924850464 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 270)) + ) + (model wrlshp/76148CD0-6DD3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SO08_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 33.1552 -51.028) + (path /539EEC0F) + (attr smd) + (fp_text reference IC1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NOR Flash" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 207 KSM_PROM_CS_N)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 208 KSM_PROM_MISO)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 244 "Net-(IC1-Pad3)")) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 210 KSM_PROM_SCLK)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 209 KSM_PROM_MOSI)) + ) + + (module Cryptech_Alpha_Footprints:_SO20W_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.356 -38.3524) + (path /539EEC0F) + (attr smd) + (fp_text reference IC2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Octal BUFFER and LINE DRIVER, 3-state" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 5.0292 5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 292 SPI_A_TRISTATE)) + (pad 2 smd rect (at 5.0292 4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 10 ARM_FPGA_CFG_CS_N)) + (pad 3 smd rect (at 5.0292 3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 125 FPGA_CFG_MISO)) + (pad 4 smd rect (at 5.0292 1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 13 ARM_FPGA_CFG_SCLK)) + (pad 5 smd rect (at 5.0292 0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 6 smd rect (at 5.0292 -0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 12 ARM_FPGA_CFG_MOSI)) + (pad 7 smd rect (at 5.0292 -1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 8 smd rect (at 5.0292 -3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 13 smd rect (at -5.0292 -3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 129 FPGA_CFG_SCLK)) + (pad 14 smd rect (at -5.0292 -1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 15 smd rect (at -5.0292 -0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 127 FPGA_CFG_MOSI)) + (pad 16 smd rect (at -5.0292 0.635 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 17 smd rect (at -5.0292 1.905 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 18 smd rect (at -5.0292 3.175 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + (pad 19 smd rect (at -5.0292 4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 293 SPI_B_TRISTATE)) + (pad 20 smd rect (at -5.0292 5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 9 smd rect (at 5.0292 -4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + (pad 10 smd rect (at 5.0292 -5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 12 smd rect (at -5.0292 -4.445 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 11 ARM_FPGA_CFG_MISO)) + (pad 11 smd rect (at -5.0292 -5.715 90) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 121 FPGA_CFG_CS_N)) + ) + + (module Cryptech_Alpha_Footprints:_SO08_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 45.5368 -25.2832) + (path /539EEC0F) + (attr smd) + (fp_text reference IC3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NOR Flash" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 5 smd rect (at 3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 172 FPGA_PROM_MOSI)) + (pad 4 smd rect (at -3.0734 1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 6 smd rect (at 3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 173 FPGA_PROM_SCLK)) + (pad 7 smd rect (at 3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 3 smd rect (at -3.0734 0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 174 FPGA_PROM_W_N)) + (pad 2 smd rect (at -3.0734 -0.635 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 171 FPGA_PROM_MISO)) + (pad 8 smd rect (at 3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 1 smd rect (at -3.0734 -1.905 270) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 170 FPGA_PROM_CS_N)) + ) + + (module Cryptech_Alpha_Footprints:_SO20W_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74.0918 -30.464) + (path /539EEC0F) + (attr smd) + (fp_text reference IC4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Octal BUFFER and LINE DRIVER, 3-state" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 11 smd rect (at 5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 218 MKM_FPGA_CS_N)) + (pad 12 smd rect (at 4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 212 MKM_AVR_MISO)) + (pad 10 smd rect (at 5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 9 smd rect (at 4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 217 MKM_CS_N)) + (pad 20 smd rect (at -5.715 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 19 smd rect (at -4.445 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 216 MKM_CONTROL_FPGA_DIS)) + (pad 18 smd rect (at -3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 217 MKM_CS_N)) + (pad 17 smd rect (at -1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 222 MKM_MISO)) + (pad 16 smd rect (at -0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 224 MKM_SCK)) + (pad 15 smd rect (at 0.635 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 220 MKM_FPGA_MOSI)) + (pad 14 smd rect (at 1.905 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 223 MKM_MOSI)) + (pad 13 smd rect (at 3.175 -5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 221 MKM_FPGA_SCK)) + (pad 8 smd rect (at 3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 222 MKM_MISO)) + (pad 7 smd rect (at 1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 224 MKM_SCK)) + (pad 6 smd rect (at 0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 5 smd rect (at -0.635 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 223 MKM_MOSI)) + (pad 4 smd rect (at -1.905 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 214 MKM_AVR_SCK)) + (pad 3 smd rect (at -3.175 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 219 MKM_FPGA_MISO)) + (pad 2 smd rect (at -4.445 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 211 MKM_AVR_CS_N)) + (pad 1 smd rect (at -5.715 5.0292) (size 0.6604 2.032) (layers F.Cu F.Paste F.Mask) + (net 215 MKM_CONTROL_AVR_ENA)) + ) + + (module Cryptech_Alpha_Footprints:_RCLAMP0502A_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 51.816 -11.0744) + (path /539EEC0F) + (attr smd) + (fp_text reference IC5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "USB protective diodes" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 299 USB_P)) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 298 USB_N)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 41 D1_N)) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 42 D1_P)) + ) + + (module Cryptech_Alpha_Footprints:_RCLAMP0502A_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 69.1134 -11.0744) + (path /539EEC0F) + (attr smd) + (fp_text reference IC6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "USB protective diodes" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 smd rect (at 0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 2 DM_P)) + (pad 5 smd rect (at 0 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 4 smd rect (at -0.5 0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 3 DM_N)) + (pad 3 smd rect (at -0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 296 USB_MGMT_N)) + (pad 2 smd rect (at 0 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0.5 -0.725 270) (size 0.85 0.3) (layers F.Cu F.Paste F.Mask) + (net 297 USB_MGMT_P)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 22.78379 -20.4216) + (path /539EEC0F) + (attr smd) + (fp_text reference J1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "STM32 SWD connector" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask)) + (pad 5 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 278 NRST)) + (pad 4 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 295 SWDIO)) + (pad 3 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 294 SWDCLK)) + (pad 1 thru_hole rect (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_a-sl254-ea-g06mp1.wrl + (offset (xyz 0.006349999904632569 0.08635999870300293 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 360)) + ) + (model wrlshp/670BFB14-85C2.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.04639 -12.5222) + (path /539EEC0F) + (attr smd) + (fp_text reference J2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 206 FT_VREGIN)) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 299 USB_P)) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 298 USB_N)) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 195 FT_RXD1)) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 197 FT_TXD1)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0.009905999851226806 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74.90459 -12.5222) + (path /539EEC0F) + (attr smd) + (fp_text reference J3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 6 thru_hole circle (at 2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 184 FT_MGMT_TXD1)) + (pad 5 thru_hole circle (at 2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 182 FT_MGMT_RXD1)) + (pad 4 thru_hole circle (at 0 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 296 USB_MGMT_N)) + (pad 3 thru_hole circle (at 0 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 297 USB_MGMT_P)) + (pad 2 thru_hole circle (at -2.54 -1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 1 thru_hole rect (at -2.54 1.27) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0.009905999851226806 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_694106301002_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 20 18.4) + (path /539EEC0F) + (attr smd) + (fp_text reference JP1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth Power Connector 5.5x2.1mm Barrel" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole oval (at 4.8 -10.6 90) (size 4.5 2) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole oval (at 0 -7.8 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 1 thru_hole oval (at 0 -13.6 90) (size 2 4.5) (drill 0.8) (layers *.Cu *.Paste *.Mask) + (net 284 PWR_18V)) + (model wrlshp/PJ-002A.wrl + (offset (xyz 0.0551179991722107 -0.01193799982070923 6.499999602379799)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 180 270)) + ) + (model wrlshp/51D2E761-0F4D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLS-2_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 64.6468 -91.7448) + (path /539EEC0F) + (attr smd) + (fp_text reference JP2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Wurth 2pins connector (for jumper)" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 245 "Net-(JP2-Pad2)")) + (pad 1 thru_hole rect (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 5 15V_LDO_ENABLE)) + (model "wrlshp/User Library-Header1x2.wrl" + (offset (xyz 5.675121914768218 11.80693582267761 -6.799998997874261)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/3416A7AC-A52A.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 89.117 -31.1658) + (path /539EEC0F) + (attr smd) + (fp_text reference JP3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 212 MKM_AVR_MISO)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 4 3V3_BATT)) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 214 MKM_AVR_SCK)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 39 AVR_RESET)) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 90)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLS-3_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 88.67933 1.5) + (path /539EEC0F) + (attr smd) + (fp_text reference JP4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Standard 3-pin 0.1\" header. Use with straight break away headers (SKU : PRT-00116), right angle break away headers (PRT-00553), swiss pins (PRT-00743), machine pins (PRT-00117), and female headers (PRT-00115). Molex polarized connector foot print use with SKU : PRT-08232 with associated crimp pins and housings." (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 thru_hole circle (at 2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 2 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 4 3V3_BATT)) + (pad 1 thru_hole rect (at -2.54 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_aw_108_03-t.wrl + (offset (xyz 0.05003799924850464 0.05003799924850464 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 0)) + ) + (model wrlshp/836C6F64-A2E5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-6_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 18.25 -29.475) + (path /539EEC0F) + (attr smd) + (fp_text reference JP7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "2x3 .1\" header" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at -1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 122 FPGA_CFG_CTRL_ARM_ENA)) + (pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 292 SPI_A_TRISTATE)) + (pad 3 thru_hole circle (at -1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 123 FPGA_CFG_CTRL_FPGA_DIS)) + (pad 4 thru_hole circle (at 1.27 0 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 293 SPI_B_TRISTATE)) + (pad 5 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 174 FPGA_PROM_W_N)) + (pad 6 thru_hole circle (at 1.27 2.54 270) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_awl254-dg-g06d.wrl + (offset (xyz 0 -0.009905999851226806 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 90)) + ) + (model wrlshp/B3089A96-FA19.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 45.5142 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 246 "Net-(LED1-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 41.51419 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 247 "Net-(LED2-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 39.51419 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 248 "Net-(LED3-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 43.5142 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 249 "Net-(LED4-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 34.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 250 "Net-(LED9-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 30.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 251 "Net-(LED10-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 28.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED11 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 252 "Net-(LED11-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 32.35 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED12 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 253 "Net-(LED12-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 74 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED13 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 254 "Net-(LED13-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 130 FPGA_DONE_INT)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 52.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED14 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RED LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 255 "Net-(LED14-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 56.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED15 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 256 "Net-(LED15-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 54.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED16 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "YELLOW LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 257 "Net-(LED16-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 50.05 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED17 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "BLUE LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 258 "Net-(LED17-Pad1)")) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_VD_0603_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 76.13225 16) + (path /539EEC0F) + (attr smd) + (fp_text reference LED18 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "GREEN LED" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 260 "Net-(LED18-Pad2)")) + (pad 1 smd rect (at 0 -0.8) (size 1 0.8) (layers F.Cu F.Paste F.Mask) + (net 259 "Net-(LED18-Pad1)")) + (model wrlshp/A9F03225-78F3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 72.452 -95.2388) + (path /539EEC0F) + (attr smd) + (fp_text reference Q1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 245 "Net-(JP2-Pad2)")) + (pad 2 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 261 "Net-(Q1-Pad1)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 90.3732 -92.7862) + (path /539EEC0F) + (attr smd) + (fp_text reference Q2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 277 NOISE_OUT)) + (pad 2 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 276 NOISE_IN)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 28.3 -34.975) + (path /539EEC0F) + (attr smd) + (fp_text reference Q3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Abracon 25MHz 10pF 4-pin 3.2 x 2.5mm crystal" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at 1.1176 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.0922 -0.8636) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 280 OSC_OUT)) + (pad 2 smd rect (at -1.0922 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1176 0.8382 180) (size 1.397 1.1938) (layers B.Cu B.Paste B.Mask) + (net 228 "Net-(C17-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 89.3064 -73.0504) + (path /539EEC0F) + (attr smd) + (fp_text reference Q4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at -1.1 0 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 155 FPGA_INIT_B_INT)) + (pad 2 smd rect (at 1.1 -0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1 0.95 180) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 156 FPGA_INIT_B)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_ASF_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 67.9704 -84.709) + (path /539EEC0F) + (attr smd) + (fp_text reference Q5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at -1.0922 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 3 smd rect (at -1.0922 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 263 "Net-(Q5-Pad3)")) + (pad 1 smd rect (at 1.1302 -1.2524 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 262 "Net-(Q5-Pad1)")) + (pad 2 smd rect (at 1.1302 1.2954 270) (size 1.7018 1.4986) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 15.7398 -42.4106) + (path /539EEC0F) + (attr smd) + (fp_text reference Q6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "OnSemi FET" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.1 -0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 283 POK_VCCO)) + (pad 2 smd rect (at -1.1 0.95) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 1.1 0) (size 1.2 0.8) (layers F.Cu F.Paste F.Mask) + (net 260 "Net-(LED18-Pad2)")) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz -0.1259839981079102 -0 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 90)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 27.5 -81.4) + (path /539EEC0F) + (attr smd) + (fp_text reference R1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 1%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 284 PWR_18V)) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 264 "Net-(R1-Pad1)")) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 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B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 83.82 -87.7454) + (path /539EEC0F) + (attr smd) + (fp_text reference S1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "WE-SHC Shielding cabinet" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 10.2616 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 -10.3886 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 7.83 90) (size 3.302 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 9.1186 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -9.1 -11.5316 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -9.1 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 9.1186 8.98 90) (size 1.016 3.302) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 3.7592 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 3.7592 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -3.75 8.98 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -3.75 -11.5316 90) (size 1.016 2.6162) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at 10.2616 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 2.48 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -10.25 -5.0292 90) (size 2.6162 1.016) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_TACTILE_SWITCH_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 62.8 -5.3608) + (path /539EEC0F) + (attr smd) + (fp_text reference S2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Tacktile switch" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad G1 smd rect (at 2.517 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad G2 smd rect (at -2.535 0 270) (size 1.016 0.45) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad B2 smd rect (at -1.8542 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad B1 smd rect (at -1.8542 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad A1 smd rect (at 1.85 2.2098 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask)) + (pad A2 smd rect (at 1.85 -2.2 180) (size 0.6096 1.016) (layers F.Cu F.Paste F.Mask) + (net 38 AVR_PANIC)) + ) + + (module Cryptech_Alpha_Footprints:_PLS-8_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 40.3 -1.3) + (path /539EEC0F) + (attr smd) + (fp_text reference SV1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 thru_hole circle (at 8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 1 thru_hole rect (at -8.89 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at -6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 161 FPGA_JTAG_TCK)) + (pad 3 thru_hole circle (at -3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 164 FPGA_JTAG_TMS)) + (pad 4 thru_hole circle (at -1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 162 FPGA_JTAG_TDI)) + (pad 5 thru_hole circle (at 1.27 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 163 FPGA_JTAG_TDO)) + (pad 6 thru_hole circle (at 3.81 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 7 thru_hole circle (at 6.35 0) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (model wrlshp/PLS-8.wrl + (offset (xyz 8.889999866485596 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/A962434E-CFE5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-16_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 59.58299 -97.7646) + (path /539EEC0F) + (attr smd) + (fp_text reference SV2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 141 FPGA_GPIO_A_7)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 140 FPGA_GPIO_A_6)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 139 FPGA_GPIO_A_5)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 138 FPGA_GPIO_A_4)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 137 FPGA_GPIO_A_3)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 136 FPGA_GPIO_A_2)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 135 FPGA_GPIO_A_1)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 134 FPGA_GPIO_A_0)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 180)) + ) + (model wrlshp/B280C847-2543.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_PLD-16_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 36.79919 -97.7646) + (path /539EEC0F) + (attr smd) + (fp_text reference SV3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "PIN HEADER 0.1\"" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 thru_hole rect (at 8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 2 thru_hole circle (at 8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 3 thru_hole circle (at 6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 4 thru_hole circle (at 6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 303 VCCO_3V3)) + (pad 5 thru_hole circle (at 3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 6 thru_hole circle (at 3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 7 thru_hole circle (at 1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 142 FPGA_GPIO_B_0)) + (pad 8 thru_hole circle (at 1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 143 FPGA_GPIO_B_1)) + (pad 9 thru_hole circle (at -1.27 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 144 FPGA_GPIO_B_2)) + (pad 10 thru_hole circle (at -1.27 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 145 FPGA_GPIO_B_3)) + (pad 11 thru_hole circle (at -3.81 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 12 thru_hole circle (at -3.81 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 7 GND)) + (pad 13 thru_hole circle (at -6.35 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 146 FPGA_GPIO_B_4)) + (pad 14 thru_hole circle (at -6.35 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 147 FPGA_GPIO_B_5)) + (pad 15 thru_hole circle (at -8.89 -1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 148 FPGA_GPIO_B_6)) + (pad 16 thru_hole circle (at -8.89 1.27 180) (size 1.5 1.5) (drill 1) (layers *.Cu *.Paste *.Mask) + (net 149 FPGA_GPIO_B_7)) + (model wrlshp/pin_header_awl254-dg-g16d.wrl + (offset (xyz -0.006349999904632569 -0.03632199945449829 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 90 360 180)) + ) + (model wrlshp/B280C847-2543.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 90.2208 -88.1634) + (path /539EEC0F) + (attr smd) + (fp_text reference T1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 3 smd rect (at 0 1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 288 RAW_NOISE)) + (pad 2 smd rect (at 0.95 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 1 smd rect (at -0.95 -1.1 270) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 277 NOISE_OUT)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 -0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 360)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 84.201 -82.7532) + (path /539EEC0F) + (attr smd) + (fp_text reference T2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "NPN Transistor" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 8 "Net-(C15-Pad2)")) + (pad 2 smd rect (at -0.95 1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd rect (at 0 -1.1 90) (size 1.2 0.8) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (model "wrlshp/SW3dPS-3-lead sot23-3.wrl" + (offset (xyz 0 0.1259839981079102 0.3499992947435379)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/04B9CA18-3B1B.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_B1,27_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 88.3158 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference TP1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Test pad" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad TP smd circle (at 0 0) (size 1.27 1.27) (layers B.Cu B.Paste B.Mask) + (net 288 RAW_NOISE)) + ) + + (module Cryptech_Alpha_Footprints:_B1,27_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.1436 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference TP2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Test pad" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad TP smd circle (at 0 0) (size 1.27 1.27) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + ) + + (module Cryptech_Alpha_Footprints:_NDY_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 22.2758 -78.2828) + (path /539EEC0F) + (attr smd) + (fp_text reference U1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 -6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 2 smd rect (at 0 -5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 284 PWR_18V)) + (pad 3 smd rect (at 0 -3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 4 smd rect (at 0 -2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 265 "Net-(R3-Pad2)")) + (pad 5 smd rect (at 0 -1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 6 smd rect (at 0 0 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 7 smd rect (at 0 1.27 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 266 "Net-(R8-Pad1)")) + (pad TP1 smd rect (at -9.525 0 90) (size 9.144 13.3858) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 8 smd rect (at 0 2.54 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 225 "Net-(C5-Pad1)")) + (pad 9 smd rect (at 0 3.81 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask)) + (pad 10 smd rect (at 0 5.08 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 11 smd rect (at 0 6.35 180) (size 2.413 0.8636) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + ) + + (module Cryptech_Alpha_Footprints:_TSOT-8-23_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 70.5 -89.75) + (path /539EEC0F) + (attr smd) + (fp_text reference U2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Micropower, Low Noise, 100mA LDO, Linear Regulator" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.3 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 5 15V_LDO_ENABLE)) + (pad 2 smd rect (at -1.3 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.3 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 4 smd rect (at -1.3 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at 1.3208 0.9906) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 284 PWR_18V)) + (pad 6 smd rect (at 1.3208 0.3302) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 6 15V_STABLE)) + (pad 7 smd rect (at 1.3208 -0.325) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 226 "Net-(C11-Pad1)")) + (pad 8 smd rect (at 1.3208 -0.975) (size 1.2446 0.4064) (layers F.Cu F.Paste F.Mask) + (net 227 "Net-(C12-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_SOT-23-5_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 77.3684 -85.1408) + (path /539EEC0F) + (attr smd) + (fp_text reference U3 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Single Inverter with Schmitt-Trigger Input" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 5 smd rect (at -1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 4 smd rect (at -1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 43 DIGITIZED_NOISE)) + (pad 3 smd rect (at 1.35 0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 2 smd rect (at 1.35 0 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask) + (net 9 AMPLIFIED)) + (pad 1 smd oval (at 1.35 -0.95 90) (size 0.65 1.1) (layers B.Cu B.Paste B.Mask)) + (model "wrlshp/User Library-SOT23-5-1.wrl" + (at (xyz 0 0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 180)) + ) + (model wrlshp/612DFB50-5309.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSQFP50P3000X3000X160-208N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 48.6918 -32.6136) + (path /539EEC0F) + (attr smd) + (fp_text reference U4 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 208 smd oval (at -12.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad 207 smd oval (at -12.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad 206 smd oval (at -11.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 106 FMC_NBL3)) + (pad 205 smd oval (at -11.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 105 FMC_NBL2)) + (pad 204 smd oval (at -10.75 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 203 smd oval (at -10.25 14.75) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + 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270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 30 smd oval (at -14.75 -1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 29 smd oval (at -14.75 -1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 28 smd oval (at -14.75 -0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 27 smd oval (at -14.75 -0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 122 FPGA_CFG_CTRL_ARM_ENA)) + (pad 26 smd oval (at -14.75 0.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 25 smd oval (at -14.75 0.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 24 smd oval (at -14.75 1.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad 23 smd oval (at -14.75 1.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad 22 smd oval (at -14.75 2.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad 21 smd oval (at -14.75 2.75 270) (size 0.3 1.2) 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(layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad 10 smd oval (at -14.75 8.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 9 smd oval (at -14.75 8.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 8 smd oval (at -14.75 9.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 7 smd oval (at -14.75 9.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 6 smd oval (at -14.75 10.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 267 "Net-(R32-Pad2)")) + (pad 5 smd oval (at -14.75 10.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_A22)) + (pad 4 smd oval (at -14.75 11.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_A21)) + (pad 3 smd oval (at -14.75 11.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_A20)) + (pad 2 smd oval (at -14.75 12.25 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_A19)) + (pad 1 smd oval (at -14.75 12.75 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_A23)) + (model wrlshp/1B9BC620-BA33.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSSOP50P1180X120-86N_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 86.1704 -49.8264) + (path /539EEC0F) + (attr smd) + (fp_text reference U5 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 44 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 45 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 95 FMC_D24)) + (pad 46 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 47 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 96 FMC_D25)) + (pad 48 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 97 FMC_D26)) + (pad 49 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 50 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 98 FMC_D27)) + (pad 51 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 99 FMC_D28)) + (pad 52 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 53 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 100 FMC_D29)) + (pad 54 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 101 FMC_D30)) + (pad 55 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 56 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 102 FMC_D31)) + (pad 57 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 58 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 59 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 106 FMC_NBL3)) + (pad 60 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 47 FMC_A3)) + (pad 61 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 48 FMC_A4)) + (pad 62 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 49 FMC_A5)) + (pad 63 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 50 FMC_A6)) + (pad 64 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 51 FMC_A7)) + (pad 65 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 52 FMC_A8)) + (pad 66 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 53 FMC_A9)) + (pad 67 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 112 FMC_SDCKE0)) + (pad 68 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 114 FMC_SDCLK)) + (pad 69 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 56 FMC_A12)) + (pad 70 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 71 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 104 FMC_NBL1)) + (pad 72 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 73 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 74 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 79 FMC_D8)) + (pad 75 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 76 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 80 FMC_D9)) + (pad 77 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 81 FMC_D10)) + (pad 78 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 79 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 82 FMC_D11)) + (pad 80 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 83 FMC_D12)) + (pad 81 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 82 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 84 FMC_D13)) + (pad 83 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 85 FMC_D14)) + (pad 84 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 85 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 86 FMC_D15)) + (pad 86 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 43 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 42 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 94 FMC_D23)) + (pad 41 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 40 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 93 FMC_D22)) + (pad 39 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 92 FMC_D21)) + (pad 38 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 37 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 91 FMC_D20)) + (pad 36 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 90 FMC_D19)) + (pad 35 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 34 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 89 FMC_D18)) + (pad 33 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 88 FMC_D17)) + (pad 32 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 31 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 87 FMC_D16)) + (pad 30 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 28 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 105 FMC_NBL2)) + (pad 27 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 46 FMC_A2)) + (pad 26 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 45 FMC_A1)) + (pad 25 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 44 FMC_A0)) + (pad 24 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 54 FMC_A10)) + (pad 23 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 59 FMC_A15)) + (pad 22 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 58 FMC_A14)) + (pad 21 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 55 FMC_A11)) + (pad 20 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 116 FMC_SDNE0)) + (pad 19 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 118 FMC_SDNRAS)) + (pad 18 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 115 FMC_SDNCAS)) + (pad 17 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 119 FMC_SDNWE)) + (pad 16 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 103 FMC_NBL0)) + (pad 15 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 14 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 13 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 78 FMC_D7)) + (pad 12 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 11 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 77 FMC_D6)) + (pad 10 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 76 FMC_D5)) + (pad 9 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 75 FMC_D4)) + (pad 7 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 74 FMC_D3)) + (pad 6 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 73 FMC_D2)) + (pad 4 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 72 FMC_D1)) + (pad 3 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 71 FMC_D0)) + (pad 1 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (model wrlshp/D87FE1D2-D8B7.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_TSSOP50P1180X120-86N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 80.6704 -49.8264) + (path /539EEC0F) + (attr smd) + (fp_text reference U6 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at -5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 2 smd oval (at -5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad 3 smd oval (at -5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 4 smd oval (at -5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad 5 smd oval (at -5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad 6 smd oval (at -5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 7 smd oval (at -5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad 8 smd oval (at -5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad 9 smd oval (at -5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 10 smd oval (at -5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad 11 smd oval (at -5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad 12 smd oval (at -5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 13 smd oval (at -5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad 14 smd oval (at -5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at -5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 16 smd oval (at -5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 103 FMC_NBL0)) + (pad 17 smd oval (at -5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 119 FMC_SDNWE)) + (pad 18 smd oval (at -5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 115 FMC_SDNCAS)) + (pad 19 smd oval (at -5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 118 FMC_SDNRAS)) + (pad 20 smd oval (at -5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 117 FMC_SDNE1)) + (pad 21 smd oval (at -5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad 22 smd oval (at -5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad 23 smd oval (at -5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad 24 smd oval (at -5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad 25 smd oval (at -5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_A0)) + (pad 26 smd oval (at -5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_A1)) + (pad 27 smd oval (at -5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_A2)) + (pad 28 smd oval (at -5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 105 FMC_NBL2)) + (pad 29 smd oval (at -5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 30 smd oval (at -5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 31 smd oval (at -5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad 32 smd oval (at -5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at -5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad 34 smd oval (at -5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad 35 smd oval (at -5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 36 smd oval (at -5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad 37 smd oval (at -5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad 38 smd oval (at -5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 39 smd oval (at -5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad 40 smd oval (at -5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad 41 smd oval (at -5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 42 smd oval (at -5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad 43 smd oval (at -5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 86 smd oval (at 5.75 10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 85 smd oval (at 5.75 10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad 84 smd oval (at 5.75 9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 83 smd oval (at 5.75 9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad 82 smd oval (at 5.75 8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad 81 smd oval (at 5.75 8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 80 smd oval (at 5.75 7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad 79 smd oval (at 5.75 7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 82 FMC_D11)) + (pad 78 smd oval (at 5.75 6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 77 smd oval (at 5.75 6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad 76 smd oval (at 5.75 5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad 75 smd oval (at 5.75 5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 74 smd oval (at 5.75 4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad 73 smd oval (at 5.75 4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 72 smd oval (at 5.75 3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 71 smd oval (at 5.75 3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 104 FMC_NBL1)) + (pad 70 smd oval (at 5.75 2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 69 smd oval (at 5.75 2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad 68 smd oval (at 5.75 1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 114 FMC_SDCLK)) + (pad 67 smd oval (at 5.75 1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 113 FMC_SDCKE1)) + (pad 66 smd oval (at 5.75 0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad 65 smd oval (at 5.75 0 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad 64 smd oval (at 5.75 -0.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad 63 smd oval (at 5.75 -1 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad 62 smd oval (at 5.75 -1.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad 61 smd oval (at 5.75 -2 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad 60 smd oval (at 5.75 -2.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad 59 smd oval (at 5.75 -3 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 106 FMC_NBL3)) + (pad 58 smd oval (at 5.75 -3.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 57 smd oval (at 5.75 -4 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask)) + (pad 56 smd oval (at 5.75 -4.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 102 FMC_D31)) + (pad 55 smd oval (at 5.75 -5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 54 smd oval (at 5.75 -5.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad 53 smd oval (at 5.75 -6 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad 52 smd oval (at 5.75 -6.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 51 smd oval (at 5.75 -7 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad 50 smd oval (at 5.75 -7.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad 49 smd oval (at 5.75 -8 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad 48 smd oval (at 5.75 -8.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad 47 smd oval (at 5.75 -9 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad 46 smd oval (at 5.75 -9.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 45 smd oval (at 5.75 -10 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad 44 smd oval (at 5.75 -10.5 270) (size 0.3 1.2) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (model wrlshp/D87FE1D2-D8B7.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOIC127P600X175-8N_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.6 -43.45) + (path /539EEC0F) + (attr smd) + (fp_text reference U7 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "RTCC, I2C, 1K EE, 64B SRAM, 8SOIC" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 8 smd rect (at 2.6924 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (pad 7 smd rect (at 2.6924 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 289 RTC_MFP)) + (pad 6 smd rect (at 2.6924 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 290 RTC_SCL)) + (pad 5 smd rect (at 2.6924 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 291 RTC_SDA)) + (pad 4 smd rect (at -2.7178 1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -2.7178 0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 2 smd rect (at -2.7178 -0.635) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 230 "Net-(C71-Pad2)")) + (pad 1 smd rect (at -2.7178 -1.905) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask) + (net 229 "Net-(C70-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-48_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 13.8186 -9.636) + (path /539EEC0F) + (attr smd) + (fp_text reference U8 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "INTERFACE, USB - UART/FIFO" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 48 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 47 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 46 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 45 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 43 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 42 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 41 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 40 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 206 FT_VREGIN)) + (pad 39 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 38 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 203 FT_VCCORE)) + (pad 37 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 201 FT_VCCA)) + (pad 36 smd rect (at -4.05 2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 35 smd rect (at -4.05 2.25001 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 34 smd rect (at -4.05 1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 193 FT_RESET)) + (pad 33 smd rect (at -4.05 1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -4.05 0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -4.05 0.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at -4.05 -0.24999 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at -4.05 -0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at -4.05 -1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at -4.05 -1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at -4.05 -2.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 25 smd rect (at -4.05 -2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 24 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 23 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 22 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 21 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 18 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 17 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 178 FT_DTR)) + (pad 16 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 177 FT_CTS)) + (pad 15 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 194 FT_RTS)) + (pad 14 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 195 FT_RXD1)) + (pad 13 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 197 FT_TXD1)) + (pad 12 smd rect (at 4.05 -2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 199 FT_VCC3V3)) + (pad 11 smd rect (at 4.05 -2.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 10 smd rect (at 4.05 -1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 9 smd rect (at 4.05 -1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 8 smd rect (at 4.05 -0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 205 FT_VPLL)) + (pad 7 smd rect (at 4.05 -0.24999 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 299 USB_P)) + (pad 6 smd rect (at 4.05 0.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 298 USB_N)) + (pad 5 smd rect (at 4.05 0.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 191 FT_REF)) + (pad 4 smd rect (at 4.05 1.25 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 4.05 1.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 204 FT_VPHY)) + (pad 2 smd rect (at 4.05 2.25001 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 232 "Net-(C78-Pad2)")) + (pad 1 smd rect (at 4.05 2.75 270) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 231 "Net-(C75-Pad2)")) + (model wrlshp/SW3dPS-LQFP48.wrl + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 270)) + ) + (model wrlshp/6B6B27F8-B7AC.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-48_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 86.3854 -17.8496) + (path /539EEC0F) + (attr smd) + (fp_text reference U9 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "INTERFACE, USB - UART/FIFO" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 233 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 234 "Net-(C93-Pad2)")) + (pad 3 smd rect (at -1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 187 FT_MGMT_VPHY)) + (pad 4 smd rect (at -1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 5 smd rect (at -0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 190 FT_REF1)) + (pad 6 smd rect (at -0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 296 USB_MGMT_N)) + (pad 7 smd rect (at 0.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 297 USB_MGMT_P)) + (pad 8 smd rect (at 0.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 188 FT_MGMT_VPLL)) + (pad 9 smd rect (at 1.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 10 smd rect (at 1.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 11 smd rect (at 2.25 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 12 smd rect (at 2.75 4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 13 smd rect (at 4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 184 FT_MGMT_TXD1)) + (pad 14 smd rect (at 4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 182 FT_MGMT_RXD1)) + (pad 15 smd rect (at 4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 181 FT_MGMT_RTS)) + (pad 16 smd rect (at 4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 179 FT_MGMT_CTS)) + (pad 17 smd rect (at 4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 180 FT_MGMT_DTR)) + (pad 18 smd rect (at 4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 19 smd rect (at 4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 20 smd rect (at 4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 21 smd rect (at 4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 22 smd rect (at 4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 23 smd rect (at 4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 24 smd rect (at 4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 25 smd rect (at 2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 26 smd rect (at 2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 27 smd rect (at 1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 28 smd rect (at 1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 29 smd rect (at 0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 30 smd rect (at 0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 31 smd rect (at -0.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 32 smd rect (at -0.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 33 smd rect (at -1.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 34 smd rect (at -1.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 192 FT_RESET1)) + (pad 35 smd rect (at -2.25 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 36 smd rect (at -2.75 -4.05 180) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 37 smd rect (at -4.05 -2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 200 FT_VCCA1)) + (pad 38 smd rect (at -4.05 -2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 202 FT_VCCORE1)) + (pad 39 smd rect (at -4.05 -1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 40 smd rect (at -4.05 -1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 189 FT_MGMT_VREGIN)) + (pad 41 smd rect (at -4.05 -0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 42 smd rect (at -4.05 -0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 43 smd rect (at -4.05 0.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 44 smd rect (at -4.05 0.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 45 smd rect (at -4.05 1.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask)) + (pad 46 smd rect (at -4.05 1.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 186 FT_MGMT_VCC3V3)) + (pad 47 smd rect (at -4.05 2.25 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 48 smd rect (at -4.05 2.75 90) (size 0.3 1.8) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model wrlshp/SW3dPS-LQFP48.wrl + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 360 360 0)) + ) + (model wrlshp/6B6B27F8-B7AC.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_LQFP-32_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 53.0832 -38.55) + (path /539EEC0F) + (attr smd) + (fp_text reference U10 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "IC, MCU, 8KB, FLASH, 20MHZ, TQFP-32" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at -2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 20 AVR_GPIO_2)) + (pad 2 smd rect (at -2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 21 AVR_GPIO_3)) + (pad 3 smd rect (at -1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 22 AVR_GPIO_4)) + (pad 4 smd rect (at -0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 5 smd rect (at 0.4 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 6 smd rect (at 1.2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 23 AVR_GPIO_5)) + (pad 7 smd rect (at 2 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 24 AVR_GPIO_6)) + (pad 8 smd rect (at 2.8 4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 25 AVR_GPIO_7)) + (pad 9 smd rect (at 4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 34 AVR_LED1)) + (pad 10 smd rect (at 4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 35 AVR_LED2)) + (pad 11 smd rect (at 4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 36 AVR_LED3)) + (pad 12 smd rect (at 4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 37 AVR_LED4)) + (pad 13 smd rect (at 4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 38 AVR_PANIC)) + (pad 14 smd rect (at 4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 211 MKM_AVR_CS_N)) + (pad 15 smd rect (at 4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 215 MKM_CONTROL_AVR_ENA)) + (pad 16 smd rect (at 4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 216 MKM_CONTROL_FPGA_DIS)) + (pad 17 smd rect (at 2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 26 AVR_GPIO_ARM_0)) + (pad 18 smd rect (at 2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 4 3V3_BATT)) + (pad 19 smd rect (at 1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 27 AVR_GPIO_ARM_1)) + (pad 20 smd rect (at 0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 28 AVR_GPIO_ARM_2)) + (pad 21 smd rect (at -0.4 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 22 smd rect (at -1.2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 29 AVR_GPIO_ARM_3)) + (pad 23 smd rect (at -2 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 30 AVR_GPIO_FPGA_0)) + (pad 24 smd rect (at -2.8 -4.475 180) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 31 AVR_GPIO_FPGA_1)) + (pad 25 smd rect (at -4.475 -2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 32 AVR_GPIO_FPGA_2)) + (pad 26 smd rect (at -4.475 -2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 33 AVR_GPIO_FPGA_3)) + (pad 27 smd rect (at -4.475 -1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 213 MKM_AVR_MOSI)) + (pad 28 smd rect (at -4.475 -0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 212 MKM_AVR_MISO)) + (pad 29 smd rect (at -4.475 0.4 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 39 AVR_RESET)) + (pad 30 smd rect (at -4.475 1.2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 214 MKM_AVR_SCK)) + (pad 31 smd rect (at -4.475 2 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 18 AVR_GPIO_0)) + (pad 32 smd rect (at -4.475 2.8 90) (size 0.55 1.55) (layers F.Cu F.Paste F.Mask) + (net 19 AVR_GPIO_1)) + (model "wrlshp/User Library-sot358-1.wrl" + (offset (xyz 0 -0.01066799983978271 0.7000011294870376)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/590BE70C-A1C3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_SOIC127P600X175-8N_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 80.4418 -30.718) + (path /539EEC0F) + (attr smd) + (fp_text reference U12 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "64K SPI Bus Low-Power Serial SRAM,SOIC-8" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -1.905 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 217 MKM_CS_N)) + (pad 2 smd rect (at -0.635 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 222 MKM_MISO)) + (pad 3 smd rect (at 0.635 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd rect (at 1.905 -2.7178 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 5 smd rect (at 1.905 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 223 MKM_MOSI)) + (pad 6 smd rect (at 0.635 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 224 MKM_SCK)) + (pad 7 smd rect (at -0.635 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 268 "Net-(R33-Pad2)")) + (pad 8 smd rect (at -1.905 2.6924 270) (size 1.55 0.6) (layers B.Cu B.Paste B.Mask) + (net 4 3V3_BATT)) + ) + + (module Cryptech_Alpha_Footprints:_BGA484C100P22X22_2300X2300X254_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 56.4534 -68.8848) + (path /539EEC0F) + (attr smd) + (fp_text reference U13 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Xilinx FPGA: XC7A200TFBG484" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad AB22 smd circle (at -10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 64 FMC_A20)) + (pad AB21 smd circle (at -9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 63 FMC_A19)) + (pad AB20 smd circle (at -8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 65 FMC_A21)) + (pad AB19 smd circle (at -7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AB18 smd circle (at -6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 68 FMC_A24)) + (pad AB17 smd circle (at -5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 48 FMC_A4)) + (pad AB16 smd circle (at -4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 45 FMC_A1)) + (pad AB15 smd circle (at -3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 52 FMC_A8)) + (pad AB14 smd circle (at -2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AB13 smd circle (at -1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 50 FMC_A6)) + (pad AB12 smd circle (at -0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 58 FMC_A14)) + (pad AB11 smd circle (at 0.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 75 FMC_D4)) + (pad AB10 smd circle (at 1.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 56 FMC_A12)) + (pad AB9 smd circle (at 2.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AB8 smd circle (at 3.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 59 FMC_A15)) + (pad AB7 smd circle (at 4.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 71 FMC_D0)) + (pad AB6 smd circle (at 5.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 72 FMC_D1)) + (pad AB5 smd circle (at 6.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 91 FMC_D20)) + (pad AB4 smd circle (at 7.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AB3 smd circle (at 8.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 87 FMC_D16)) + (pad AB2 smd circle (at 9.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 86 FMC_D15)) + (pad AB1 smd circle (at 10.5 10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 85 FMC_D14)) + (pad AA22 smd circle (at -10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA21 smd circle (at -9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 80 FMC_D9)) + (pad AA20 smd circle (at -8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 153 FPGA_GPIO_LED_3)) + (pad AA19 smd circle (at -7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 69 FMC_A25)) + (pad AA18 smd circle (at -6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad AA17 smd circle (at -5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AA16 smd circle (at -4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 46 FMC_A2)) + (pad AA15 smd circle (at -3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 51 FMC_A7)) + (pad AA14 smd circle (at -2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 54 FMC_A10)) + (pad AA13 smd circle (at -1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 49 FMC_A5)) + (pad AA12 smd circle (at -0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA11 smd circle (at 0.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 76 FMC_D5)) + (pad AA10 smd circle (at 1.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad AA9 smd circle (at 2.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 60 FMC_A16)) + (pad AA8 smd circle (at 3.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 61 FMC_A17)) + (pad AA7 smd circle (at 4.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad AA6 smd circle (at 5.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 111 FMC_NWE)) + (pad AA5 smd circle (at 6.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 90 FMC_D19)) + (pad AA4 smd circle (at 7.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 93 FMC_D22)) + (pad AA3 smd circle (at 8.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 89 FMC_D18)) + (pad AA2 smd circle (at 9.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad AA1 smd circle (at 10.5 9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 84 FMC_D13)) + (pad Y22 smd circle (at -10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 67 FMC_A23)) + (pad Y21 smd circle (at -9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 66 FMC_A22)) + (pad Y20 smd circle (at -8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad Y19 smd circle (at -7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y18 smd circle (at -6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 79 FMC_D8)) + (pad Y17 smd circle (at -5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 44 FMC_A0)) + (pad Y16 smd circle (at -4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 47 FMC_A3)) + (pad Y15 smd circle (at -3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad Y14 smd circle (at -2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 55 FMC_A11)) + (pad Y13 smd circle (at -1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 53 FMC_A9)) + (pad Y12 smd circle (at -0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 78 FMC_D7)) + (pad Y11 smd circle (at 0.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 77 FMC_D6)) + (pad Y10 smd circle (at 1.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad Y9 smd circle (at 2.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y8 smd circle (at 3.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y7 smd circle (at 4.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 62 FMC_A18)) + (pad Y6 smd circle (at 5.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 110 FMC_NWAIT)) + (pad Y5 smd circle (at 6.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad Y4 smd circle (at 7.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 92 FMC_D21)) + (pad Y3 smd circle (at 8.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 88 FMC_D17)) + (pad Y2 smd circle (at 9.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad Y1 smd circle (at 10.5 8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 219 MKM_FPGA_MISO)) + (pad W22 smd circle (at -10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 152 FPGA_GPIO_LED_2)) + (pad W21 smd circle (at -9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W20 smd circle (at -8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 81 FMC_D10)) + (pad W19 smd circle (at -7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 43 DIGITIZED_NOISE)) + (pad W18 smd circle (at -6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad W17 smd circle (at -5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 108 FMC_NL)) + (pad W16 smd circle (at -4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 109 FMC_NOE)) + (pad W15 smd circle (at -3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W14 smd circle (at -2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 98 FMC_D27)) + (pad W13 smd circle (at -1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad W12 smd circle (at -0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 97 FMC_D26)) + (pad W11 smd circle (at 0.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 70 FMC_CLK)) + (pad W10 smd circle (at 1.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 95 FMC_D24)) + (pad W9 smd circle (at 2.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W8 smd circle (at 3.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad W7 smd circle (at 4.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W6 smd circle (at 5.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W5 smd circle (at 6.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W4 smd circle (at 7.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad W3 smd circle (at 8.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad W2 smd circle (at 9.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 218 MKM_FPGA_CS_N)) + (pad W1 smd circle (at 10.5 7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 220 MKM_FPGA_MOSI)) + (pad V22 smd circle (at -10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V21 smd circle (at -9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad V20 smd circle (at -8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 99 FMC_D28)) + (pad V19 smd circle (at -7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V18 smd circle (at -6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 100 FMC_D29)) + (pad V17 smd circle (at -5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V16 smd circle (at -4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad V15 smd circle (at -3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V14 smd circle (at -2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V13 smd circle (at -1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V12 smd circle (at -0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 161 FPGA_JTAG_TCK)) + (pad V11 smd circle (at 0.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad V10 smd circle (at 1.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V9 smd circle (at 2.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V8 smd circle (at 3.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V7 smd circle (at 4.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad V6 smd circle (at 5.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad V5 smd circle (at 6.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 107 FMC_NE1)) + (pad V4 smd circle (at 7.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 94 FMC_D23)) + (pad V3 smd circle (at 8.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 221 MKM_FPGA_SCK)) + (pad V2 smd circle (at 9.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 57 FMC_A13)) + (pad V1 smd circle (at 10.5 6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U22 smd circle (at -10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 273 "Net-(R65-Pad1)")) + (pad U21 smd circle (at -9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U20 smd circle (at -8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 83 FMC_D12)) + (pad U19 smd circle (at -7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad U18 smd circle (at -6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U17 smd circle (at -5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U16 smd circle (at -4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U15 smd circle (at -3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U14 smd circle (at -2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U13 smd circle (at -1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 163 FPGA_JTAG_TDO)) + (pad U12 smd circle (at -0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 154 FPGA_INIT_B_INT1)) + (pad U11 smd circle (at 0.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 165 FPGA_M0)) + (pad U10 smd circle (at 1.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 166 FPGA_M1)) + (pad U9 smd circle (at 2.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 167 FPGA_M2)) + (pad U8 smd circle (at 3.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad U7 smd circle (at 4.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U6 smd circle (at 5.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U5 smd circle (at 6.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad U4 smd circle (at 7.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad U3 smd circle (at 8.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 150 FPGA_GPIO_LED_0)) + (pad U2 smd circle (at 9.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 74 FMC_D3)) + (pad U1 smd circle (at 10.5 5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 73 FMC_D2)) + (pad T22 smd circle (at -10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T21 smd circle (at -9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T20 smd circle (at -8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T19 smd circle (at -7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 120 FPGA_CFG_CS_N1)) + (pad T18 smd circle (at -6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T17 smd circle (at -5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T16 smd circle (at -4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T15 smd circle (at -3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T14 smd circle (at -2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T13 smd circle (at -1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 164 FPGA_JTAG_TMS)) + (pad T12 smd circle (at -0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T11 smd circle (at 0.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T10 smd circle (at 1.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad T9 smd circle (at 2.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T8 smd circle (at 3.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad T7 smd circle (at 4.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad T6 smd circle (at 5.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T5 smd circle (at 6.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T4 smd circle (at 7.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T3 smd circle (at 8.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad T2 smd circle (at 9.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad T1 smd circle (at 10.5 4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 151 FPGA_GPIO_LED_1)) + (pad R22 smd circle (at -10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 124 FPGA_CFG_MISO1)) + (pad R21 smd circle (at -9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 101 FMC_D30)) + (pad R20 smd circle (at -8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R19 smd circle (at -7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R18 smd circle (at -6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R17 smd circle (at -5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R16 smd circle (at -4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R15 smd circle (at -3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad R14 smd circle (at -2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R13 smd circle (at -1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 162 FPGA_JTAG_TDI)) + (pad R12 smd circle (at -0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R11 smd circle (at 0.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad R10 smd circle (at 1.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R9 smd circle (at 2.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad R8 smd circle (at 3.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad R7 smd circle (at 4.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad R6 smd circle (at 5.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R5 smd circle (at 6.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad R4 smd circle (at 7.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 96 FMC_D25)) + (pad R3 smd circle (at 8.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R2 smd circle (at 9.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad R1 smd circle (at 10.5 3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P22 smd circle (at -10.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 126 FPGA_CFG_MOSI1)) + (pad P21 smd circle (at -9.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 102 FMC_D31)) + (pad P20 smd circle (at -8.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P19 smd circle (at -7.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P18 smd circle (at -6.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad P17 smd circle (at -5.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P16 smd circle (at -4.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P15 smd circle (at -3.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P14 smd circle (at -2.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad P13 smd circle (at -1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P12 smd circle (at -0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad P11 smd circle (at 0.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad P10 smd circle (at 1.5 2.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 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180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad H14 smd circle (at -2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad H13 smd circle (at -1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad H12 smd circle (at -0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 175 FPGA_VCCAUX_1V8)) + (pad H11 smd circle (at 0.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad H10 smd circle (at 1.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad H9 smd circle (at 2.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad H8 smd circle (at 3.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 176 FPGA_VCCINT_1V0)) + (pad H7 smd circle (at 4.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad H6 smd circle (at 5.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad H5 smd circle (at 6.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad H4 smd circle (at 7.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad H3 smd circle (at 8.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad H2 smd circle (at 9.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad H1 smd circle (at 10.5 -3.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G22 smd circle (at -10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G21 smd circle (at -9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G20 smd circle (at -8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G19 smd circle (at -7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad G18 smd circle (at -6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G17 smd circle (at -5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G16 smd circle (at -4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G15 smd circle (at -3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G14 smd circle (at -2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G13 smd circle (at -1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G12 smd circle (at -0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G11 smd circle (at 0.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 130 FPGA_DONE_INT)) + (pad G10 smd circle (at 1.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G9 smd circle (at 2.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G8 smd circle (at 3.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G7 smd circle (at 4.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G6 smd circle (at 5.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G5 smd circle (at 6.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad G4 smd circle (at 7.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G3 smd circle (at 8.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G2 smd circle (at 9.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad G1 smd circle (at 10.5 -4.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F22 smd circle (at -10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad F21 smd circle (at -9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F20 smd circle (at -8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F19 smd circle (at -7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F18 smd circle (at -6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F17 smd circle (at -5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad F16 smd circle (at -4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 158 FPGA_IRQ_N_1)) + (pad F15 smd circle (at -3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F14 smd circle (at -2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 157 FPGA_IRQ_N_0)) + (pad F13 smd circle (at -1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F12 smd circle (at -0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad F11 smd circle (at 0.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad F10 smd circle (at 1.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F9 smd circle (at 2.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F8 smd circle (at 3.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F7 smd circle (at 4.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F6 smd circle (at 5.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F5 smd circle (at 6.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad F4 smd circle (at 7.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F3 smd circle (at 8.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad F2 smd circle (at 9.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad F1 smd circle (at 10.5 -5.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E22 smd circle (at -10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E21 smd circle (at -9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E20 smd circle (at -8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad E19 smd circle (at -7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E18 smd circle (at -6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E17 smd circle (at -5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 159 FPGA_IRQ_N_2)) + (pad E16 smd circle (at -4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E15 smd circle (at -3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad E14 smd circle (at -2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 134 FPGA_GPIO_A_0)) + (pad E13 smd circle (at -1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 135 FPGA_GPIO_A_1)) + (pad E12 smd circle (at -0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad E11 smd circle (at 0.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad E10 smd circle (at 1.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E9 smd circle (at 2.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad E8 smd circle (at 3.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E7 smd circle (at 4.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad E6 smd circle (at 5.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E5 smd circle (at 6.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad E4 smd circle (at 7.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad E3 smd circle (at 8.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E2 smd circle (at 9.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad E1 smd circle (at 10.5 -6.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D22 smd circle (at -10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D21 smd circle (at -9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D20 smd circle (at -8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D19 smd circle (at -7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D18 smd circle (at -6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad D17 smd circle (at -5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 133 FPGA_GCLK)) + (pad D16 smd circle (at -4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D15 smd circle (at -3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D14 smd circle (at -2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 145 FPGA_GPIO_B_3)) + (pad D13 smd circle (at -1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D12 smd circle (at -0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D11 smd circle (at 0.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D10 smd circle (at 1.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D9 smd circle (at 2.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D8 smd circle (at 3.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D7 smd circle (at 4.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D6 smd circle (at 5.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D5 smd circle (at 6.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D4 smd circle (at 7.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D3 smd circle (at 8.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad D2 smd circle (at 9.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad D1 smd circle (at 10.5 -7.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C22 smd circle (at -10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 149 FPGA_GPIO_B_7)) + (pad C21 smd circle (at -9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad C20 smd circle (at -8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 148 FPGA_GPIO_B_6)) + (pad C19 smd circle (at -7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C18 smd circle (at -6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 146 FPGA_GPIO_B_4)) + (pad C17 smd circle (at -5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C16 smd circle (at -4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C15 smd circle (at -3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 143 FPGA_GPIO_B_1)) + (pad C14 smd circle (at -2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 160 FPGA_IRQ_N_3)) + (pad C13 smd circle (at -1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 138 FPGA_GPIO_A_4)) + (pad C12 smd circle (at -0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C11 smd circle (at 0.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C10 smd circle (at 1.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C9 smd circle (at 2.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C8 smd circle (at 3.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C7 smd circle (at 4.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C6 smd circle (at 5.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C5 smd circle (at 6.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C4 smd circle (at 7.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C3 smd circle (at 8.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad C2 smd circle (at 9.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad C1 smd circle (at 10.5 -8.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad B22 smd circle (at -10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B21 smd circle (at -9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B20 smd circle (at -8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 30 AVR_GPIO_FPGA_0)) + (pad B19 smd circle (at -7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B18 smd circle (at -6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 132 FPGA_ENTROPY_DISABLE)) + (pad B17 smd circle (at -5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B16 smd circle (at -4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 144 FPGA_GPIO_B_2)) + (pad B15 smd circle (at -3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 141 FPGA_GPIO_A_7)) + (pad B14 smd circle (at -2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad B13 smd circle (at -1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 139 FPGA_GPIO_A_5)) + (pad B12 smd circle (at -0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B11 smd circle (at 0.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B10 smd circle (at 1.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B9 smd circle (at 2.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B8 smd circle (at 3.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B7 smd circle (at 4.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B6 smd circle (at 5.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B5 smd circle (at 6.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B4 smd circle (at 7.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B3 smd circle (at 8.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad B2 smd circle (at 9.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad B1 smd circle (at 10.5 -9.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A22 smd circle (at -10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A21 smd circle (at -9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 147 FPGA_GPIO_B_5)) + (pad A20 smd circle (at -8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 31 AVR_GPIO_FPGA_1)) + (pad A19 smd circle (at -7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 33 AVR_GPIO_FPGA_3)) + (pad A18 smd circle (at -6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 32 AVR_GPIO_FPGA_2)) + (pad A17 smd circle (at -5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 303 VCCO_3V3)) + (pad A16 smd circle (at -4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 142 FPGA_GPIO_B_0)) + (pad A15 smd circle (at -3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 140 FPGA_GPIO_A_6)) + (pad A14 smd circle (at -2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 137 FPGA_GPIO_A_3)) + (pad A13 smd circle (at -1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 136 FPGA_GPIO_A_2)) + (pad A12 smd circle (at -0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A11 smd circle (at 0.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A10 smd circle (at 1.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A9 smd circle (at 2.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A8 smd circle (at 3.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A7 smd circle (at 4.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A6 smd circle (at 5.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A5 smd circle (at 6.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A4 smd circle (at 7.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (pad A3 smd circle (at 8.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A2 smd circle (at 9.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad A1 smd circle (at 10.5 -10.5 180) (size 0.45 0.45) (layers B.Cu B.Paste B.Mask)) + (model wrlshp/041B98A5-F02D.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_QFN38_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 35.4584 -76.5556) + (path /539EEC0F) + (attr smd) + (fp_text reference U14 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad PAD39 smd oval (at 0 1.26 180) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 38 smd oval (at -1.905 -3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at -1.905 -2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at -1.905 -2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at -1.905 -1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 34 smd oval (at -1.905 -1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 33 smd oval (at -1.905 -0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 32 smd oval (at -1.905 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 31 smd oval (at -1.905 0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 238 "Net-(C117-Pad2)")) + (pad 30 smd oval (at -1.905 1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 235 "Net-(C115-Pad1)")) + (pad 29 smd oval (at -1.905 1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 270 "Net-(R53-Pad2)")) + (pad 28 smd oval (at -1.905 2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 281 POK_VCCAUX)) + (pad 27 smd oval (at -1.905 2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 285 PWR_ENA_VCCAUX)) + (pad 26 smd oval (at -1.905 3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 269 "Net-(R52-Pad1)")) + (pad 25 smd oval (at -1.27 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at -0.762 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at -0.254 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 22 smd oval (at 0.25 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 21 smd oval (at 0.75 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 20 smd oval (at 1.25 3.4036 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 19 smd oval (at 1.9 3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 18 smd oval (at 1.9 2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 17 smd oval (at 1.9 2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 16 smd oval (at 1.9 1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 15 smd oval (at 1.9 1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 14 smd oval (at 1.9 0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 13 smd oval (at 1.9 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 12 smd oval (at 1.9 -0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 11 smd oval (at 1.9 -1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 10 smd oval (at 1.9 -1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 9 smd oval (at 1.9 -2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 8 smd oval (at 1.9 -2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 7 smd oval (at 1.9 -3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 6 smd oval (at 1.25 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 5 smd oval (at 0.75 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 237 "Net-(C117-Pad1)")) + (pad 4 smd oval (at 0.25 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at -0.254 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at -0.762 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 1 smd oval (at -1.27 -3.4 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + ) + + (module Cryptech_Alpha_Footprints:_QFN38_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 10.8458 -41.0972) + (path /539EEC0F) + (attr smd) + (fp_text reference U15 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at 1.27 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 2 smd oval (at 0.762 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 3 smd oval (at 0.254 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 4 smd oval (at -0.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 5 smd oval (at -0.75 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 6 smd oval (at -1.25 3.4 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 7 smd oval (at -1.9 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 8 smd oval (at -1.9 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 9 smd oval (at -1.9 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 10 smd oval (at -1.9 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 11 smd oval (at -1.9 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 239 "Net-(C118-Pad1)")) + (pad 12 smd oval (at -1.9 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 13 smd oval (at -1.9 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 14 smd oval (at -1.9 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 15 smd oval (at -1.9 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 16 smd oval (at -1.9 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 17 smd oval (at -1.9 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 18 smd oval (at -1.9 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 19 smd oval (at -1.9 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 20 smd oval (at -1.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 21 smd oval (at -0.75 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 22 smd oval (at -0.25 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 0.254 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.762 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 1.27 -3.4036 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at 1.905 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 271 "Net-(R54-Pad1)")) + (pad 27 smd oval (at 1.905 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 287 PWR_ENA_VCCO)) + (pad 28 smd oval (at 1.905 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 283 POK_VCCO)) + (pad 29 smd oval (at 1.905 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 272 "Net-(R55-Pad2)")) + (pad 30 smd oval (at 1.905 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 236 "Net-(C116-Pad1)")) + (pad 31 smd oval (at 1.905 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 240 "Net-(C118-Pad2)")) + (pad 32 smd oval (at 1.905 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at 1.905 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 34 smd oval (at 1.905 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 35 smd oval (at 1.905 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 36 smd oval (at 1.905 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 37 smd oval (at 1.905 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 38 smd oval (at 1.905 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad PAD39 smd oval (at 0 -1.26) (size 2.6 1.94) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_QFN68_ (layer B.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 25.9842 -57.4802) + (path /539EEC0F) + (attr smd) + (fp_text reference U16 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd oval (at 5.5 -3.5052 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 2 smd oval (at 5.5 -3.0226 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 3 smd oval (at 5.5 -2.5146 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 4 smd oval (at 5.5 -2.0066 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 5 smd oval (at 5.5 -1.524 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 6 smd oval (at 5.5 -1.016 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 7 smd oval (at 5.5 -0.508 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 8 smd oval (at 5.5 0 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 9 smd oval (at 5.5 0.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 10 smd oval (at 5.5 1 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 11 smd oval (at 5.5 1.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 12 smd oval (at 5.5 2 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 13 smd oval (at 5.5 2.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 242 "Net-(C208-Pad1)")) + (pad 14 smd oval (at 5.5 3 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 15 smd oval (at 5.5 3.5 180) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 16 smd oval (at 4.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 17 smd oval (at 4 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 18 smd oval (at 3.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 19 smd oval (at 3 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 20 smd oval (at 2.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 21 smd oval (at 2 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 22 smd oval (at 1.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 23 smd oval (at 1 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 24 smd oval (at 0.5 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 25 smd oval (at 0 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 26 smd oval (at -0.508 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 27 smd oval (at -1.016 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 28 smd oval (at -1.524 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 29 smd oval (at -2.0066 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 30 smd oval (at -2.5146 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 31 smd oval (at -3.0226 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 32 smd oval (at -3.5052 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 33 smd oval (at -4.0132 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 34 smd oval (at -4.5212 3.9 90) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 35 smd oval (at -5.5118 3.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 36 smd oval (at -5.5118 3) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 37 smd oval (at -5.5118 2.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 38 smd oval (at -5.5118 2) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 39 smd oval (at -5.5118 1.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 40 smd oval (at -5.5118 1) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 41 smd oval (at -5.5118 0.5) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 42 smd oval (at -5.5118 0) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 43 smd oval (at -5.5118 -0.508) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 44 smd oval (at -5.5118 -1.016) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 45 smd oval (at -5.5118 -1.524) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 46 smd oval (at -5.5118 -2.0066) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 47 smd oval (at -5.5118 -2.5146) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 48 smd oval (at -5.5118 -3.0226) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 49 smd oval (at -5.5118 -3.5052) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 50 smd oval (at -4.5212 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 51 smd oval (at -4.0132 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 274 "Net-(R66-Pad1)")) + (pad 52 smd oval (at -3.5052 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 286 PWR_ENA_VCCINT)) + (pad 53 smd oval (at -3.0226 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 302 VCC_5V0)) + (pad 54 smd oval (at -2.5146 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 282 POK_VCCINT)) + (pad 55 smd oval (at -2.0066 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 56 smd oval (at -1.524 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 243 "Net-(C208-Pad2)")) + (pad 57 smd oval (at -1.016 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 58 smd oval (at -0.508 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 59 smd oval (at 0 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 241 "Net-(C207-Pad1)")) + (pad 60 smd oval (at 0.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 61 smd oval (at 1 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 62 smd oval (at 1.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask)) + (pad 63 smd oval (at 2 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 275 "Net-(R67-Pad1)")) + (pad 64 smd oval (at 2.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 65 smd oval (at 3 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 66 smd oval (at 3.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 67 smd oval (at 4 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad 68 smd oval (at 4.5 -3.9116 270) (size 0.6096 0.254) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad PAD69 smd oval (at -2.175 0.625 90) (size 5.35 2.35) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + (pad PAD70 smd oval (at 3.55 -2.65 180) (size 2.5 1.3) (layers B.Cu B.Paste B.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_XTAL3215_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 19.275 -45.6) + (path /539EEC0F) + (attr smd) + (fp_text reference X1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 32.768kHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad P$1 smd rect (at 0 -1.2192 90) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 229 "Net-(C70-Pad2)")) + (pad P$2 smd rect (at 0 1.2 270) (size 1.1176 1.905) (layers F.Cu F.Paste F.Mask) + (net 230 "Net-(C71-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 23.075 -5.5) + (path /539EEC0F) + (attr smd) + (fp_text reference Y1 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 12MHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at -0.8382 -1.1176 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 232 "Net-(C78-Pad2)")) + (pad 2 smd rect (at -0.8382 1.0922 270) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at 0.8636 1.0922 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 231 "Net-(C75-Pad2)")) + (pad 4 smd rect (at 0.8636 -1.1176 90) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + ) + + (module Cryptech_Alpha_Footprints:_CRYSTAL_3.2X2.5_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 82.525 -8.8) + (path /539EEC0F) + (attr smd) + (fp_text reference Y2 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "Crystal 12MHz" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 4 smd rect (at 1.1176 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 3 smd rect (at -1.0922 0.8636) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 233 "Net-(C90-Pad2)")) + (pad 2 smd rect (at -1.0922 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 1 smd rect (at 1.1176 -0.8382 180) (size 1.397 1.1938) (layers F.Cu F.Paste F.Mask) + (net 234 "Net-(C93-Pad2)")) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 59.4 -62.4) + (path /539EEC0F) + (attr smd) + (fp_text reference R35 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0 0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (pad 2 smd rect (at 0 -0.5 90) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 167 FPGA_M2)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 270)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 37.091 -59.1757) + (path /539EEC0F) + (attr smd) + (fp_text reference R36 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 2 smd rect (at 0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 166 FPGA_M1)) + (pad 1 smd rect (at -0.5 0) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 7 GND)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 0)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 360)) + ) + ) + + (module Cryptech_Alpha_Footprints:_R_0402_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 37.091 -60.4076) + (path /539EEC0F) + (attr smd) + (fp_text reference R37 (at 0 0) (layer F.SilkS) hide + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (fp_text value "0402 Resistor 5%" (at 0 0) (layer Cmts.User) + (effects (font (size 1.524 1.524) (thickness 0.05))) + ) + (pad 1 smd rect (at 0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 165 FPGA_M0)) + (pad 2 smd rect (at -0.5 0 180) (size 0.45 0.6) (layers F.Cu F.Paste F.Mask) + (net 303 VCCO_3V3)) + (model "wrlshp/SW3dPS-0402 SMD Resistor.wrl" + (at (xyz 0 -0 0)) + (scale (xyz 0.39370078740158 0.39370078740158 0.39370078740158)) + (rotate (xyz 270 360 180)) + ) + (model wrlshp/537E0B02-A9B3.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Cryptech_Alpha_Footprints:_DEFAULT_ (layer F.Cu) (tedit 4289BEAB) (tstamp 539EEDBF) + (at 0 0) + (path /539EEC0F) + (attr smd) + (fp_text reference "" (at 0 0) (layer F.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (fp_text value "" (at 0 0) (layer F.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.15))) + ) + (pad "" smd circle (at 65.2394 -15.597 180) (size 1 1) (layers F.Cu F.Paste F.Mask)) + (pad "" smd circle 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