diff options
| author | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:16:39 +0300 |
|---|---|---|
| committer | Pavel V. Shatov (Meister) <meisterpaul1@yandex.ru> | 2020-09-23 15:16:39 +0300 |
| commit | 03109511936e9e91a21e3616162067c07fc2048c (patch) | |
| tree | fba80d10308e42fb1481f84f2580f75047ec31ba /KiCAD/rev02_19.sch-bak | |
| parent | 59237fb52930aa5495fe25526d5269f05239282e (diff) | |
Did some cleanup, also had to re-route VCC_PLL for iCE40.
Diffstat (limited to 'KiCAD/rev02_19.sch-bak')
| -rw-r--r-- | KiCAD/rev02_19.sch-bak | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/KiCAD/rev02_19.sch-bak b/KiCAD/rev02_19.sch-bak index 5410a68..439f1c6 100644 --- a/KiCAD/rev02_19.sch-bak +++ b/KiCAD/rev02_19.sch-bak @@ -278,7 +278,7 @@ Wire Wire Line Wire Wire Line 3100 8200 1900 8200 Text GLabel 3100 8200 2 48 UnSpc ~ 0 -ICE40_GPIO_FPGA_5 +ICE40_GPIO_FPGA_7 Wire Wire Line 3100 5200 1900 5200 Text GLabel 3100 5200 2 48 UnSpc ~ 0 @@ -454,7 +454,7 @@ ICE40_GPIO_FPGA_6 Wire Wire Line 3100 8400 1900 8400 Text GLabel 3100 8400 2 48 UnSpc ~ 0 -ICE40_GPIO_FPGA_7 +ICE40_GPIO_FPGA_5 Wire Wire Line 3100 7500 1900 7500 Wire Wire Line |