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authorPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-09-23 15:14:24 +0300
committerPavel V. Shatov (Meister) <meisterpaul1@yandex.ru>2020-09-23 15:14:24 +0300
commit59237fb52930aa5495fe25526d5269f05239282e (patch)
tree713b82ce1515375b7ab5f7284a4b28e324f3a524 /KiCAD/rev02_19.sch-bak
parentdf87322e903025945ccc4607cabdca46d98318e0 (diff)
Entirely routed the design. Not useable right now, so far just reports zero
unrouted nets. Will cleanup next.
Diffstat (limited to 'KiCAD/rev02_19.sch-bak')
-rw-r--r--KiCAD/rev02_19.sch-bak36
1 files changed, 24 insertions, 12 deletions
diff --git a/KiCAD/rev02_19.sch-bak b/KiCAD/rev02_19.sch-bak
index d1feb42..5410a68 100644
--- a/KiCAD/rev02_19.sch-bak
+++ b/KiCAD/rev02_19.sch-bak
@@ -276,13 +276,9 @@ Wire Wire Line
Wire Wire Line
8500 6600 8400 6600
Wire Wire Line
- 3100 8100 1900 8100
-Text GLabel 3100 8100 2 48 UnSpc ~ 0
-ICE40_GPIO_FPGA_0
-Wire Wire Line
3100 8200 1900 8200
Text GLabel 3100 8200 2 48 UnSpc ~ 0
-ICE40_GPIO_FPGA_1
+ICE40_GPIO_FPGA_5
Wire Wire Line
3100 5200 1900 5200
Text GLabel 3100 5200 2 48 UnSpc ~ 0
@@ -454,11 +450,11 @@ FPGA_ENTROPY_DISABLE
Wire Wire Line
3100 8300 1900 8300
Text GLabel 3100 8300 2 48 UnSpc ~ 0
-ICE40_GPIO_FPGA_2
+ICE40_GPIO_FPGA_6
Wire Wire Line
3100 8400 1900 8400
Text GLabel 3100 8400 2 48 UnSpc ~ 0
-ICE40_GPIO_FPGA_3
+ICE40_GPIO_FPGA_7
Wire Wire Line
3100 7500 1900 7500
Wire Wire Line
@@ -614,13 +610,8 @@ NoConn ~ 1900 5000
NoConn ~ 1900 5100
NoConn ~ 1900 5900
NoConn ~ 1900 6000
-NoConn ~ 1900 7100
-NoConn ~ 1900 7400
NoConn ~ 1900 7600
-NoConn ~ 1900 7700
NoConn ~ 1900 7800
-NoConn ~ 1900 8000
-NoConn ~ 1900 7900
NoConn ~ 1900 8500
NoConn ~ 1900 8600
NoConn ~ 1900 8700
@@ -634,4 +625,25 @@ NoConn ~ 1900 9700
NoConn ~ 1900 9800
NoConn ~ 1900 9900
NoConn ~ 1900 6200
+Text GLabel 3100 7100 2 48 UnSpc ~ 0
+ICE40_GPIO_FPGA_4
+NoConn ~ 1900 8100
+Wire Wire Line
+ 1900 7100 3100 7100
+Text GLabel 3100 7900 2 48 UnSpc ~ 0
+ICE40_GPIO_FPGA_3
+Text GLabel 3100 8000 2 48 UnSpc ~ 0
+ICE40_GPIO_FPGA_2
+Wire Wire Line
+ 1900 7400 3100 7400
+Wire Wire Line
+ 1900 7700 3100 7700
+Wire Wire Line
+ 1900 7900 3100 7900
+Wire Wire Line
+ 1900 8000 3100 8000
+Text GLabel 3100 7400 2 48 UnSpc ~ 0
+ICE40_GPIO_FPGA_1
+Text GLabel 3100 7700 2 48 UnSpc ~ 0
+ICE40_GPIO_FPGA_0
$EndSCHEMATC