init

4 files changed, 1298 insertions, 0 deletions

diff --git a/Device/ldscripts/nucleo.ld b/Device/ldscripts/nucleo.ld
new file mode 100644
index 0000000..33cfc2a
--- /dev/null
+++ b/Device/ldscripts/nucleo.ld
@@ -0,0 +1,199 @@
+/* Linker script to configure memory regions. 
+ * Need modifying for a specific board. 
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+_estack = 0x20017FFF;
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.isr_vector))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab : 
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+		
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		_sdata = __data_start__;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+		_edata = __data_end__;
+
+	} > RAM
+
+	_sidata = LOADADDR(.data);
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		_sbss = __bss_start__;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		_ebss = __bss_end__;
+	} > RAM
+	
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+	
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Device/ldscripts/rev08.ld b/Device/ldscripts/rev08.ld
new file mode 100644
index 0000000..1b1011b
--- /dev/null
+++ b/Device/ldscripts/rev08.ld
@@ -0,0 +1,199 @@
+/* Linker script to configure memory regions. 
+ * Need modifying for a specific board. 
+ *   FLASH.ORIGIN: starting address of flash
+ *   FLASH.LENGTH: length of flash
+ *   RAM.ORIGIN: starting address of RAM bank 0
+ *   RAM.LENGTH: length of RAM bank 0
+ */
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+_estack = 0x2000FFFF;
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.isr_vector))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab : 
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+		
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		_sdata = __data_start__;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+		_edata = __data_end__;
+
+	} > RAM
+
+	_sidata = LOADADDR(.data);
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		_sbss = __bss_start__;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+		_ebss = __bss_end__;
+	} > RAM
+	
+	.heap (COPY):
+	{
+		__end__ = .;
+		PROVIDE(end = .);
+		*(.heap*)
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+	
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/Device/startup_stm32f401xc.s b/Device/startup_stm32f401xc.s
new file mode 100644
index 0000000..d19fd94
--- /dev/null
+++ b/Device/startup_stm32f401xc.s
@@ -0,0 +1,450 @@
+/**

+  ******************************************************************************

+  * @file      startup_stm32f401xc.s

+  * @author    MCD Application Team

+  * @version   V2.1.0

+  * @date      19-June-2014

+  * @brief     STM32F401xCxx Devices vector table for Atollic TrueSTUDIO toolchain.

+  *            This module performs:

+  *                - Set the initial SP

+  *                - Set the initial PC == Reset_Handler,

+  *                - Set the vector table entries with the exceptions ISR address

+  *                - Branches to main in the C library (which eventually

+  *                  calls main()).

+  *            After Reset the Cortex-M4 processor is in Thread mode,

+  *            priority is Privileged, and the Stack is set to Main.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>

+  *

+  * Redistribution and use in source and binary forms, with or without modification,

+  * are permitted provided that the following conditions are met:

+  *   1. Redistributions of source code must retain the above copyright notice,

+  *      this list of conditions and the following disclaimer.

+  *   2. Redistributions in binary form must reproduce the above copyright notice,

+  *      this list of conditions and the following disclaimer in the documentation

+  *      and/or other materials provided with the distribution.

+  *   3. Neither the name of STMicroelectronics nor the names of its contributors

+  *      may be used to endorse or promote products derived from this software

+  *      without specific prior written permission.

+  *

+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+  *

+  ******************************************************************************

+  */

+

+  .syntax unified

+  .cpu cortex-m4

+  .fpu softvfp

+  .thumb

+

+.global  g_pfnVectors

+.global  Default_Handler

+

+/* start address for the initialization values of the .data section.

+defined in linker script */

+.word  _sidata

+/* start address for the .data section. defined in linker script */

+.word  _sdata

+/* end address for the .data section. defined in linker script */

+.word  _edata

+/* start address for the .bss section. defined in linker script */

+.word  _sbss

+/* end address for the .bss section. defined in linker script */

+.word  _ebss

+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */

+

+/**

+ * @brief  This is the code that gets called when the processor first

+ *          starts execution following a reset event. Only the absolutely

+ *          necessary set is performed, after which the application

+ *          supplied main() routine is called.

+ * @param  None

+ * @retval : None

+*/

+

+    .section  .text.Reset_Handler

+  .weak  Reset_Handler

+  .type  Reset_Handler, %function

+Reset_Handler:

+  ldr   sp, =_estack      /* set stack pointer */

+

+/* Copy the data segment initializers from flash to SRAM */

+  movs  r1, #0

+  b  LoopCopyDataInit

+

+CopyDataInit:

+  ldr  r3, =_sidata

+  ldr  r3, [r3, r1]

+  str  r3, [r0, r1]

+  adds  r1, r1, #4

+

+LoopCopyDataInit:

+  ldr  r0, =_sdata

+  ldr  r3, =_edata

+  adds  r2, r0, r1

+  cmp  r2, r3

+  bcc  CopyDataInit

+  ldr  r2, =_sbss

+  b  LoopFillZerobss

+/* Zero fill the bss segment. */

+FillZerobss:

+  movs  r3, #0

+  str  r3, [r2], #4

+

+LoopFillZerobss:

+  ldr  r3, = _ebss

+  cmp  r2, r3

+  bcc  FillZerobss

+

+/* Call the clock system intitialization function.*/

+  bl  SystemInit

+/* Call static constructors */

+    bl __libc_init_array

+/* Call the application's entry point.*/

+  bl  main

+  bx  lr

+.size  Reset_Handler, .-Reset_Handler

+

+/**

+ * @brief  This is the code that gets called when the processor receives an

+ *         unexpected interrupt.  This simply enters an infinite loop, preserving

+ *         the system state for examination by a debugger.

+ * @param  None

+ * @retval None

+*/

+    .section  .text.Default_Handler,"ax",%progbits

+Default_Handler:

+Infinite_Loop:

+  b  Infinite_Loop

+  .size  Default_Handler, .-Default_Handler

+/******************************************************************************

+*

+* The minimal vector table for a Cortex M3. Note that the proper constructs

+* must be placed on this to ensure that it ends up at physical address

+* 0x0000.0000.

+*

+*******************************************************************************/

+   .section  .isr_vector,"a",%progbits

+  .type  g_pfnVectors, %object

+  .size  g_pfnVectors, .-g_pfnVectors

+

+g_pfnVectors:

+  .word  _estack

+  .word  Reset_Handler

+  .word  NMI_Handler

+  .word  HardFault_Handler

+  .word  MemManage_Handler

+  .word  BusFault_Handler

+  .word  UsageFault_Handler

+  .word  0

+  .word  0

+  .word  0

+  .word  0

+  .word  SVC_Handler

+  .word  DebugMon_Handler

+  .word  0

+  .word  PendSV_Handler

+  .word  SysTick_Handler

+

+  /* External Interrupts */

+  .word     WWDG_IRQHandler                   /* Window WatchDog              */

+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */

+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */

+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */

+  .word     FLASH_IRQHandler                  /* FLASH                        */

+  .word     RCC_IRQHandler                    /* RCC                          */

+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */

+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */

+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */

+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */

+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */

+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */

+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */

+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */

+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */

+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */

+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */

+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */

+  .word     ADC_IRQHandler                    /* ADC1                         */

+  .word     0               				          /* Reserved                     */

+  .word     0              					          /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */

+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */

+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */

+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */

+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */

+  .word     TIM2_IRQHandler                   /* TIM2                         */

+  .word     TIM3_IRQHandler                   /* TIM3                         */

+  .word     TIM4_IRQHandler                   /* TIM4                         */

+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */

+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */

+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */

+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */

+  .word     SPI1_IRQHandler                   /* SPI1                         */

+  .word     SPI2_IRQHandler                   /* SPI2                         */

+  .word     USART1_IRQHandler                 /* USART1                       */

+  .word     USART2_IRQHandler                 /* USART2                       */

+  .word     0               				          /* Reserved                     */

+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */

+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */

+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */

+  .word     0                                 /* Reserved     				        */

+  .word     0                                 /* Reserved       			        */

+  .word     0                                 /* Reserved 					          */

+  .word     0                                 /* Reserved                     */

+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */

+  .word     0                                 /* Reserved                     */

+  .word     SDIO_IRQHandler                   /* SDIO                         */

+  .word     TIM5_IRQHandler                   /* TIM5                         */

+  .word     SPI3_IRQHandler                   /* SPI3                         */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */

+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */

+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */

+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */

+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */

+  .word     0                    			        /* Reserved                     */

+  .word     0              					          /* Reserved                     */

+  .word     0              					          /* Reserved                     */

+  .word     0             					          /* Reserved                     */

+  .word     0              					          /* Reserved                     */

+  .word     0              					          /* Reserved                     */

+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */

+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */

+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */

+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */

+  .word     USART6_IRQHandler                 /* USART6                       */

+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */

+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     FPU_IRQHandler                    /* FPU                          */

+  .word     0                                 /* Reserved                     */

+  .word     0                                 /* Reserved                     */

+  .word     SPI4_IRQHandler                   /* SPI4                         */

+

+/*******************************************************************************

+*

+* Provide weak aliases for each Exception handler to the Default_Handler.

+* As they are weak aliases, any function with the same name will override

+* this definition.

+*

+*******************************************************************************/

+   .weak      NMI_Handler

+   .thumb_set NMI_Handler,Default_Handler

+

+   .weak      HardFault_Handler

+   .thumb_set HardFault_Handler,Default_Handler

+

+   .weak      MemManage_Handler

+   .thumb_set MemManage_Handler,Default_Handler

+

+   .weak      BusFault_Handler

+   .thumb_set BusFault_Handler,Default_Handler

+

+   .weak      UsageFault_Handler

+   .thumb_set UsageFault_Handler,Default_Handler

+

+   .weak      SVC_Handler

+   .thumb_set SVC_Handler,Default_Handler

+

+   .weak      DebugMon_Handler

+   .thumb_set DebugMon_Handler,Default_Handler

+

+   .weak      PendSV_Handler

+   .thumb_set PendSV_Handler,Default_Handler

+

+   .weak      SysTick_Handler

+   .thumb_set SysTick_Handler,Default_Handler

+

+   .weak      WWDG_IRQHandler

+   .thumb_set WWDG_IRQHandler,Default_Handler

+

+   .weak      PVD_IRQHandler

+   .thumb_set PVD_IRQHandler,Default_Handler

+

+   .weak      TAMP_STAMP_IRQHandler

+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler

+

+   .weak      RTC_WKUP_IRQHandler

+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler

+

+   .weak      FLASH_IRQHandler

+   .thumb_set FLASH_IRQHandler,Default_Handler

+

+   .weak      RCC_IRQHandler

+   .thumb_set RCC_IRQHandler,Default_Handler

+

+   .weak      EXTI0_IRQHandler

+   .thumb_set EXTI0_IRQHandler,Default_Handler

+

+   .weak      EXTI1_IRQHandler

+   .thumb_set EXTI1_IRQHandler,Default_Handler

+

+   .weak      EXTI2_IRQHandler

+   .thumb_set EXTI2_IRQHandler,Default_Handler

+

+   .weak      EXTI3_IRQHandler

+   .thumb_set EXTI3_IRQHandler,Default_Handler

+

+   .weak      EXTI4_IRQHandler

+   .thumb_set EXTI4_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream0_IRQHandler

+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream1_IRQHandler

+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream2_IRQHandler

+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream3_IRQHandler

+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream4_IRQHandler

+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream5_IRQHandler

+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream6_IRQHandler

+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler

+

+   .weak      ADC_IRQHandler

+   .thumb_set ADC_IRQHandler,Default_Handler

+

+   .weak      EXTI9_5_IRQHandler

+   .thumb_set EXTI9_5_IRQHandler,Default_Handler

+

+   .weak      TIM1_BRK_TIM9_IRQHandler

+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler

+

+   .weak      TIM1_UP_TIM10_IRQHandler

+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler

+

+   .weak      TIM1_TRG_COM_TIM11_IRQHandler

+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler

+

+   .weak      TIM1_CC_IRQHandler

+   .thumb_set TIM1_CC_IRQHandler,Default_Handler

+

+   .weak      TIM2_IRQHandler

+   .thumb_set TIM2_IRQHandler,Default_Handler

+

+   .weak      TIM3_IRQHandler

+   .thumb_set TIM3_IRQHandler,Default_Handler

+

+   .weak      TIM4_IRQHandler

+   .thumb_set TIM4_IRQHandler,Default_Handler

+

+   .weak      I2C1_EV_IRQHandler

+   .thumb_set I2C1_EV_IRQHandler,Default_Handler

+

+   .weak      I2C1_ER_IRQHandler

+   .thumb_set I2C1_ER_IRQHandler,Default_Handler

+

+   .weak      I2C2_EV_IRQHandler

+   .thumb_set I2C2_EV_IRQHandler,Default_Handler

+

+   .weak      I2C2_ER_IRQHandler

+   .thumb_set I2C2_ER_IRQHandler,Default_Handler

+

+   .weak      SPI1_IRQHandler

+   .thumb_set SPI1_IRQHandler,Default_Handler

+

+   .weak      SPI2_IRQHandler

+   .thumb_set SPI2_IRQHandler,Default_Handler

+

+   .weak      USART1_IRQHandler

+   .thumb_set USART1_IRQHandler,Default_Handler

+

+   .weak      USART2_IRQHandler

+   .thumb_set USART2_IRQHandler,Default_Handler

+

+   .weak      EXTI15_10_IRQHandler

+   .thumb_set EXTI15_10_IRQHandler,Default_Handler

+

+   .weak      RTC_Alarm_IRQHandler

+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler

+

+   .weak      OTG_FS_WKUP_IRQHandler

+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler

+

+   .weak      DMA1_Stream7_IRQHandler

+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler

+

+   .weak      SDIO_IRQHandler

+   .thumb_set SDIO_IRQHandler,Default_Handler

+

+   .weak      TIM5_IRQHandler

+   .thumb_set TIM5_IRQHandler,Default_Handler

+

+   .weak      SPI3_IRQHandler

+   .thumb_set SPI3_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream0_IRQHandler

+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream1_IRQHandler

+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream2_IRQHandler

+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream3_IRQHandler

+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream4_IRQHandler

+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler

+

+   .weak      OTG_FS_IRQHandler

+   .thumb_set OTG_FS_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream5_IRQHandler

+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream6_IRQHandler

+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler

+

+   .weak      DMA2_Stream7_IRQHandler

+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler

+

+   .weak      USART6_IRQHandler

+   .thumb_set USART6_IRQHandler,Default_Handler

+

+   .weak      I2C3_EV_IRQHandler

+   .thumb_set I2C3_EV_IRQHandler,Default_Handler

+

+   .weak      I2C3_ER_IRQHandler

+   .thumb_set I2C3_ER_IRQHandler,Default_Handler

+

+   .weak      FPU_IRQHandler

+   .thumb_set FPU_IRQHandler,Default_Handler

+

+   .weak      SPI4_IRQHandler

+   .thumb_set SPI4_IRQHandler,Default_Handler

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+

diff --git a/Device/startup_stm32f401xe.s b/Device/startup_stm32f401xe.s
new file mode 100644
index 0000000..cddd397
--- /dev/null
+++ b/Device/startup_stm32f401xe.s
@@ -0,0 +1,450 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f401xe.s
+  * @author    MCD Application Team
+  * @version   V2.0.0
+  * @date      18-February-2014 
+  * @brief     STM32F401xExx Devices vector table for Atollic TrueSTUDIO toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+  ldr   sp, =_estack    		 /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     0               				  /* Reserved                      */                         
+  .word     0              					  /* Reserved                     */                          
+  .word     0                                 /* Reserved                     */                          
+  .word     0                                 /* Reserved                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     0               				  /* Reserved                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     0                                 /* Reserved     				  */         
+  .word     0                                 /* Reserved       			  */         
+  .word     0                                 /* Reserved 					  */
+  .word     0                                 /* Reserved                     */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     0                                 /* Reserved                     */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     0                    			  /* Reserved                     */                   
+  .word     0              					  /* Reserved                     */                     
+  .word     0              					  /* Reserved                     */                          
+  .word     0             					  /* Reserved                     */                          
+  .word     0              					  /* Reserved                     */                          
+  .word     0              					  /* Reserved                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */                         
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     0                                 /* Reserved                     */                   
+  .word     0                                 /* Reserved                     */
+  .word     SPI4_IRQHandler                   /* SPI4                         */     
+                    
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+      
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  
+
+   .weak      SPI4_IRQHandler                  
+   .thumb_set SPI4_IRQHandler,Default_Handler 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+