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authorJoachim Strömbergson <joachim@assured.se>2019-01-25 11:05:05 +0100
committerJoachim Strömbergson <joachim@assured.se>2019-01-25 11:05:05 +0100
commit15580aab680a1be1450a7ac42a833c70e5fbff1d (patch)
treef2f405831315f581cdb746c3633fc7fe05631133
Adding Von Neumann decorrelator core to Cryptech.HEADmaster
-rw-r--r--LICENSE29
-rw-r--r--README.md26
-rw-r--r--src/rtl/vndecorrelator.v165
-rw-r--r--src/tb/tb_vndecorrelator.v273
-rw-r--r--toolruns/Makefile81
5 files changed, 574 insertions, 0 deletions
diff --git a/LICENSE b/LICENSE
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index 0000000..65e4e7e
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,29 @@
+Author: Joachim Strömbergson
+Copyright (c) 2019, NORDUnet A/S
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+- Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+- Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+- Neither the name of the NORDUnet nor the names of its contributors may
+ be used to endorse or promote products derived from this software
+ without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/README.md b/README.md
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index 0000000..41214d6
--- /dev/null
+++ b/README.md
@@ -0,0 +1,26 @@
+vndecorrelator
+==============
+
+# Introduction
+A Verilog implementation of a von Neumann decorrelator, generally called
+a conditioner or whitening function. This tiny module consumes entropy
+bits and outputs decorrelated bits.
+
+The [Von Neumann decorrelator](http://www1.spms.ntu.edu.sg/~kkhoongm/Entropy.pdf)
+consumes pairs of bits and outputs bits based on the pattern in th bit pairs:
+
+- 00 and 11: No output of a bit.
+- 10 and 01: Output the first bit in the pair
+
+In the best case with random bits, the output bitrate will be 1/4. For
+heavily biased input bits, the rate will be much slower. When used with
+a broken entropy source that is stuck at zero or one, no bits will be
+emitted.
+
+This implementation operates on streams of single bits and creates pairs
+internally.
+
+
+# Status
+
+Implementation done. Tested in FPGA designs and works.
diff --git a/src/rtl/vndecorrelator.v b/src/rtl/vndecorrelator.v
new file mode 100644
index 0000000..57aabfb
--- /dev/null
+++ b/src/rtl/vndecorrelator.v
@@ -0,0 +1,165 @@
+//======================================================================
+//
+// vndecorrelator.v
+// ----------------
+// von Neumann decorrelator for bits. The module consumes bits
+// and for every two bits consume will either emit zero or one bits.
+//
+//
+// Author: Joachim Strömbergson
+// Copyright (c) 2019, NORDUnet A/S
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module vndecorrelator(
+ input wire clk,
+ input wire reset_n,
+
+ input wire data_in,
+ input wire syn_in,
+
+ output wire data_out,
+ output wire syn_out
+ );
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter CTRL_IDLE = 1'b0;
+ parameter CTRL_BITS = 1'b1;
+
+
+ //----------------------------------------------------------------
+ // Registers including update variables and write enable.
+ //----------------------------------------------------------------
+ reg data_in_reg;
+ reg data_in_we;
+
+ reg data_out_reg;
+ reg data_out_we;
+
+ reg syn_out_reg;
+ reg syn_out_new;
+
+ reg vndecorr_ctrl_reg;
+ reg vndecorr_ctrl_new;
+ reg vndecorr_ctrl_we;
+
+
+ //----------------------------------------------------------------
+ // Concurrent connectivity for ports etc.
+ //----------------------------------------------------------------
+ assign data_out = data_out_reg;
+ assign syn_out = syn_out_reg;
+
+
+ //----------------------------------------------------------------
+ // reg_update
+ //----------------------------------------------------------------
+ always @ (posedge clk or negedge reset_n)
+ begin
+ if (!reset_n)
+ begin
+ data_in_reg <= 1'b0;
+ data_out_reg <= 1'b0;
+ syn_out_reg <= 1'b0;
+ vndecorr_ctrl_reg <= CTRL_IDLE;
+ end
+ else
+ begin
+ syn_out_reg <= syn_out_new;
+
+ if (data_in_we)
+ begin
+ data_in_reg <= data_in;
+ end
+
+ if (data_out_we)
+ begin
+ data_out_reg <= data_in;
+ end
+
+ if (vndecorr_ctrl_we)
+ begin
+ vndecorr_ctrl_reg <= vndecorr_ctrl_new;
+ end
+ end
+ end // reg_update
+
+
+ //----------------------------------------------------------------
+ // vndecorr_logic
+ //
+ // The logic implementing the von Neumann decorrelator by waiting
+ // for subsequent bits and comparing them to determine if both
+ // bits should just be discarded or one of them also emitted.
+ //----------------------------------------------------------------
+ always @*
+ begin : vndecorr_logic
+ data_in_we = 1'b0;
+ data_out_we = 1'b0;
+ syn_out_new = 1'b0;
+ vndecorr_ctrl_new = CTRL_IDLE;
+ vndecorr_ctrl_we = 1'b0;
+
+ case (vndecorr_ctrl_reg)
+ CTRL_IDLE:
+ begin
+ if (syn_in)
+ begin
+ data_in_we = 1'b1;
+ vndecorr_ctrl_new = CTRL_BITS;
+ vndecorr_ctrl_we = 1'b1;
+ end
+ end
+
+ CTRL_BITS:
+ begin
+ if (syn_in)
+ begin
+ if (data_in != data_in_reg)
+ begin
+ data_out_we = 1'b1;
+ syn_out_new = 1'b1;
+ end
+
+ vndecorr_ctrl_new = CTRL_IDLE;
+ vndecorr_ctrl_we = 1'b1;
+ end
+ end
+ endcase // case (vndecorr_ctrl_reg)
+ end // vndecorr_logic
+
+endmodule // vndecorrelator
+
+//======================================================================
+// EOF vndecorrelator.v
+//======================================================================
diff --git a/src/tb/tb_vndecorrelator.v b/src/tb/tb_vndecorrelator.v
new file mode 100644
index 0000000..9afe843
--- /dev/null
+++ b/src/tb/tb_vndecorrelator.v
@@ -0,0 +1,273 @@
+//======================================================================
+//
+// tb_vndecorrelator.v
+// -------------------
+// Testbench for the von Neumann decorrelator.
+//
+//
+// Author: Joachim Strömbergson
+// Copyright (c) 2019, NORDUnet A/S
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+
+//------------------------------------------------------------------
+// Test module.
+//------------------------------------------------------------------
+module tb_vndecorrelator();
+
+
+ //----------------------------------------------------------------
+ // Internal constant and parameter definitions.
+ //----------------------------------------------------------------
+ parameter DEBUG = 1;
+
+ parameter CLK_HALF_PERIOD = 1;
+ parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
+
+
+ //----------------------------------------------------------------
+ // Register and Wire declarations.
+ //----------------------------------------------------------------
+ reg [31 : 0] cycle_ctr;
+ reg [31 : 0] error_ctr;
+ reg [31 : 0] tc_ctr;
+
+ reg tb_clk;
+ reg tb_reset_n;
+ reg tb_data_in;
+ reg tb_syn_in;
+ wire tb_data_out;
+ wire tb_syn_out;
+
+
+ //----------------------------------------------------------------
+ // Device Under Test.
+ //----------------------------------------------------------------
+ vndecorrelator dut(
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
+
+ .data_in(tb_data_in),
+ .syn_in(tb_syn_in),
+
+ .data_out(tb_data_out),
+ .syn_out(tb_syn_out)
+ );
+
+
+ //----------------------------------------------------------------
+ // clk_gen
+ //
+ // Always running clock generator process.
+ //----------------------------------------------------------------
+ always
+ begin : clk_gen
+ #CLK_HALF_PERIOD;
+ tb_clk = !tb_clk;
+ end // clk_gen
+
+
+ //--------------------------------------------------------------------
+ // dut_monitor
+ //
+ // Monitor displaying information every cycle.
+ // Includes the cycle counter.
+ //--------------------------------------------------------------------
+ always @ (posedge tb_clk)
+ begin : dut_monitor
+ cycle_ctr = cycle_ctr + 1;
+
+ if (DEBUG)
+ begin
+ $display("cycle = %016x:", cycle_ctr);
+ $display("reset_n = 0x%01x", dut.reset_n);
+ $display("data_in = 0x%01x, syn_in = 0x%01x", dut.data_in, dut.syn_in);
+ $display("data_out = 0x%01x, syn_out = 0x%01x", dut.data_out, dut.syn_out);
+ $display("ctrl = 0x%01x", dut.vndecorr_ctrl_reg);
+ $display("");
+ end
+ end // dut_monitor
+
+
+ //----------------------------------------------------------------
+ // reset_dut()
+ //
+ // Toggle reset to put the DUT into a well known state.
+ //----------------------------------------------------------------
+ task reset_dut;
+ begin
+ $display("*** Toggle reset.");
+ tb_reset_n = 0;
+ #(2 * CLK_PERIOD);
+ tb_reset_n = 1;
+ end
+ endtask // reset_dut
+
+
+ //----------------------------------------------------------------
+ // init_sim()
+ //
+ // Initialize all counters and testbed functionality as well
+ // as setting the DUT inputs to defined values.
+ //----------------------------------------------------------------
+ task init_sim;
+ begin
+ cycle_ctr = 0;
+ error_ctr = 0;
+ tc_ctr = 0;
+
+ tb_clk = 0;
+ tb_reset_n = 1;
+ tb_data_in = 0;
+ tb_syn_in = 0;
+ end
+ endtask // init_sim
+
+
+ //----------------------------------------------------------------
+ // decorrelation_test
+ //
+ // The main test functionality.
+ //----------------------------------------------------------------
+ initial
+ begin : decorrelation_test
+ $display(" -= Testbench for the vpn Neumann decorrelator =-");
+ $display(" ===============================================");
+ $display("");
+
+ init_sim();
+ reset_dut();
+
+ // TC1: 1, 0 directly after eachother. Should emit 0.
+ #(10 *CLK_PERIOD);
+ $display("TC1: 1 directly followed by 0. Should emit 0.");
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ // TC2: 0, 1 directly after eachother. Should generate 1.
+ #(10 *CLK_PERIOD);
+ $display("TC2: 0 directly followed by 1. Should emit 1.");
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ // TC3: 0, 0 directly after eachother. Should emit nothing.
+ #(10 *CLK_PERIOD);
+ $display("TC3: 0 directly followed by 0. Should emit nothing.");
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ // TC4: 1, 1 directly after eachother. Should enmit nothing.
+ #(10 *CLK_PERIOD);
+ $display("TC4: 1 directly followed by 1. Should emit nothing.");
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ // TC5: 1, 0 with 10 cycles in between. Should emit 0.
+ #(10 *CLK_PERIOD);
+ $display("TC5: 1 and later 0. Should emit 0.");
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+ #(10 *CLK_PERIOD);
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ // TC6: 0, 1 with 10 cycles in between. Should emit 1.
+ #(10 *CLK_PERIOD);
+ $display("TC6: 0 and later 1. Should emit 1.");
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+ #(10 *CLK_PERIOD);
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ // TC7: 0, 0 with 10 cycles in between. Should emit nothing.
+ #(10 *CLK_PERIOD);
+ $display("TC7: 0 and later 0. Should emit nothing.");
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+ #(10 *CLK_PERIOD);
+ tb_data_in = 0;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ // TC8: 1, 1 with 10 cycles in between. Should emit nothing.
+ #(10 *CLK_PERIOD);
+ $display("TC8: 1 and later 1. Should emit nothing.");
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+ #(10 *CLK_PERIOD);
+ tb_data_in = 1;
+ tb_syn_in = 1;
+ #(CLK_PERIOD);
+ tb_syn_in = 0;
+
+ $display("");
+ $display("*** von Neumann decorrelation simulation done. ***");
+ $finish;
+ end // decorrelation_test
+endmodule // tb_vndecorrelator
+
+//======================================================================
+// EOF tb_vndecorrelator.v
+//======================================================================
diff --git a/toolruns/Makefile b/toolruns/Makefile
new file mode 100644
index 0000000..cea7041
--- /dev/null
+++ b/toolruns/Makefile
@@ -0,0 +1,81 @@
+#===================================================================
+#
+# Makefile
+# --------
+# Makefile for building von Neumann decorrelation simulation.
+#
+#
+# Author: Joachim Strömbergson
+# Copyright (c) 2019, NORDUnet A/S
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# - Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# - Neither the name of the NORDUnet nor the names of its contributors may
+# be used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#===================================================================
+
+CORE_SRC=../src/rtl/vndecorrelator.v
+CORE_TB_SRC=../src/tb/tb_vndecorrelator.v
+
+CC = iverilog
+CC_FLAGS= -Wall
+
+LINT=verilator
+LINT_FLAGS = +1364-2001ext+ --lint-only -Wall -Wno-fatal -Wno-DECLFILENAME
+
+
+all: core.sim
+
+
+core.sim: $(CORE_TB_SRC) $(CORE_SRC)
+ $(CC) $(CC_FLAGS) -o core.sim $(CORE_SRC) $(CORE_TB_SRC)
+
+
+sim-core: core.sim
+ ./core.sim
+
+
+lint: $(CORE_SRC)
+ $(LINT) $(LINT_FLAGS) $(CORE_SRC)
+
+
+clean:
+ rm *.sim
+
+
+help:
+ @echo "Supported targets:"
+ @echo "------------------"
+ @echo "all: Build all simulation targets."
+ @echo "core.sim Build the core simulation target."
+ @echo "sim-core: Run core level simulation."
+ @echo "lint: Run the linter on the source"
+ @echo "clean: Delete all generared files."
+
+
+#===================================================================
+# EOF Makefile
+#===================================================================