A Verilog implementation of a von Neumann decorrelator, generally called
a conditioner or whitening function. This tiny module consumes entropy
bits and outputs decorrelated bits.
The Von Neumann decorrelator
consumes pairs of bits and outputs bits based on the pattern in th bit pairs:
- 00 and 11: No output of a bit.
- 10 and 01: Output the first bit in the pair
In the best case with random bits, the output bitrate will be 1/4. For
heavily biased input bits, the rate will be much slower. When used with
a broken entropy source that is stuck at zero or one, no bits will be
emitted.
This implementation operates on streams of single bits and creates pairs
internally.
Implementation done. Tested in FPGA designs and works.