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//======================================================================
//
// tb_fpga_mkm_spi_slave.v
// -----------------------
// Testbench for the SPI slave interface for the FPGA based
// Master Key Memory (MKM).
//
//
// Author: Joachim Strombergson
// Copyright (c) 2019, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_fpga_mkm_spi_slave();
//----------------------------------------------------------------
// Parameters.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Variables, regs and wires.
//----------------------------------------------------------------
integer cycle_ctr;
integer error_ctr;
integer tc_ctr;
reg tb_clk;
reg tb_ss;
reg tb_sclk;
reg tb_mosi;
wire tb_miso;
wire tb_spi_active;
wire tb_rx_byte_available;
wire [7 : 0] tb_rx_byte;
reg tb_tx_byte_available;
reg [7 : 0] tb_tx_byte;
wire tb_tx_byte_ack;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
fpga_mkm_spi_slave dut(
.clk(tb_clk),
.ss(tb_ss),
.sclk(tb_sclk),
.mosi(tb_mosi),
.miso(tb_miso),
.spi_active(tb_spi_active),
.rx_byte_available(tb_rx_byte_available),
.rx_byte(tb_rx_byte),
.tx_byte_available(tb_tx_byte_available),
.tx_byte(tb_tx_byte),
.tx_byte_ack(tb_tx_byte_ack)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#(CLK_HALF_PERIOD);
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
end
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim
//
// Initialize DUT inputs, test case counters, clock etc.
//----------------------------------------------------------------
task init_sim;
begin : init_sim
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 1'h0;
tb_ss = 1'h1;
tb_sclk = 1'h0;
tb_mosi = 1'h0;
end
endtask // init_sim
//----------------------------------------------------------------
// wait_cycles
//----------------------------------------------------------------
task wait_cycles (input integer cycles);
begin : wait_cycles
#(cycles);
end
endtask // wait_cycles
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
initial
begin
$display(" -= Testbench for fpga_mkm_spi_slave started =-");
$display(" =============================================");
$display("");
init_sim();
wait_cycles(100);
display_test_results();
$display("");
$display(" -= Testbench for fpga_mkm_spi_slave completed =-");
$display(" ===============================================");
$finish;
end
endmodule // tb_fpga_mkm_spi_slave
//======================================================================
// EOF tb_fpga_mkm_spi_slave.v
//======================================================================
|
