src/rtl/top.v


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module top (
            input wire clk_in,
            output wire rled1,
            output wire rled2,
            output wire rled3,
            output wire rled4,
            output wire gled5
           );

  reg [31 : 0] counter_reg = 32'b0;

  assign rled1 = counter[21];
  assign rled2 = counter[22];
  assign rled3 = counter[23];
  assign rled4 = counter[24];
  assign gled5 = counter[25];

  always @ (posedge hwclk)
    begin
      counter_reg <= counter_reg + 1;
    end

endmodule // top