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//======================================================================
//
// fpga_mkm_spi_slave.v
// --------------------
// SPI Slave for the FPGA based Master Key Memory (MKM).
//
// The interface captures serial data from the master and provides
// it as bytes to the interface host. Any response from the host
// to be transmitted to the master should be given as bytes.
//
// It is the responsibility of the host to send as much response as
// the master expects.
//
// The clk driving the interface must be >> sclk to allow for
// the cycles needed to perform state handling, parsing etc.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2019, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fpga_mkm_spi_slave(
input wire clk,
input wire ss,
input wire sclk,
input wire mosi,
output wire miso,
output wire rx_byte_available,
output wire rx_byte_ack,
output wire [7 : 0] rx_byte,
input wire tx_byte_available,
output wire tx_byte_ack,
output wire tx_byte_error,
input wire [7 : 0] tx_byte
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg ss_sample0_reg;
reg ss_sample1_reg;
reg ss_reg;
reg sclk_sample0_reg;
reg sclk_sample1_reg;
reg sclk_reg;
reg mosi_sample0_reg;
reg mosi_sample1_reg;
reg mosi_reg;
reg [7 : 0] rx_byte_reg;
reg [7 : 0] rx_byte_new;
reg rx_byte_we;
reg [2 : 0] rx_bit_ctr_reg;
reg [2 : 0] rx_bit_ctr_new;
reg rx_bit_ctr_we;
reg rx_bit_ctr_rst;
reg rx_bit_ctr_inc;
reg rx_byte_available_reg;
reg rx_byte_available_new;
reg rx_byte_available_we;
reg [7 : 0] tx_byte_reg;
reg [7 : 0] tx_byte_new;
reg tx_byte_we;
reg tx_byte_set;
reg tx_byte_shift;
reg [2 : 0] tx_bit_ctr_reg;
reg [2 : 0] tx_bit_ctr_new;
reg tx_bit_ctr_we;
reg tx_bit_ctr_rst;
reg tx_bit_ctr_inc;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign miso = tx_byte_reg[7];
assign rx_byte_available = rx_byte_available_reg;
assign rx_byte = rx_byte_reg;
assign tx_byte_ack = 1'h0;
assign tx_byte_error = 1'h0;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
ss_sample0_reg <= ss;
ss_sample1_reg <= ss_sample0_reg;
ss_reg <= ss_sample1_reg;
sclk_sample0_reg <= sclk;
sclk_sample1_reg <= sclk_sample0_reg;
sclk_reg <= sclk_sample1_reg;
mosi_sample0_reg <= mosi;
mosi_sample1_reg <= mosi_sample0_reg;
mosi_reg <= mosi_sample1_reg;
if (rx_byte_we)
rx_byte_reg <= rx_byte_new;
if (rx_bit_ctr_we)
rx_bit_ctr_reg <= rx_bit_ctr_new;
if (rx_byte_available_we)
rx_byte_available_reg <= rx_byte_available_new;
if (tx_byte_we)
tx_byte_reg <= tx_byte_new;
if (tx_bit_ctr_we)
tx_bit_ctr_reg <= tx_bit_ctr_new;
end
//----------------------------------------------------------------
// spi_slave_ctrl_fsm
//----------------------------------------------------------------
always @*
begin : spi_slave_ctrl_fsm
end
endmodule // fpga_mkm_spi_slave
//======================================================================
// EOF fpga_mkm_spi_slave.v
//======================================================================
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