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//======================================================================
//
// fpga_mkm.v
// ----------
// Top level module for the FPGA based Master Key Memory (MKM).
//
//
// Author: Joachim Strombergson
// Copyright (c) 2019, NORDUnet A/S
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// - Neither the name of the NORDUnet nor the names of its contributors may
// be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module fpga_mkm(
input wire clk,
input wire sclk,
input wire mosi,
output wire miso,
// Tamper and alarm.
input wire tamper,
output wire alarm,
// We will use red LEDs to indicate tamper event.
output wire rled1,
output wire rled2,
output wire rled3,
output wire rled4,
// We will use the green LED to indicate loaded key.
output wire gled5
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 0;
localparam CTRL_ALARM = 1;
localparam CTRL_DONE = 3;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [21 : 0] alarm_counter_reg = 22'h0;
reg alarm_reg = 1'h0;
reg alarm_new;
reg alarm_we;
reg key_loaded_reg = 1'h0;
reg key_loaded_new;
reg key_loaded_we;
reg miso_reg = 1'h0;
reg [1 : 0] fpga_mkm_ctrl_reg = CTRL_IDLE;
reg [1 : 0] fpga_mkm_ctrl_new;
reg fpga_mkm_ctrl_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign rled1 = alarm_counter_reg[21];
assign rled2 = alarm_counter_reg[21];
assign rled3 = alarm_counter_reg[21];
assign rled4 = alarm_counter_reg[21];
assign gled5 = key_loaded_reg;
assign miso = miso_reg;
assign alarm = alarm_reg;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
alarm_counter_reg <= alarm_counter_reg + 1;
if (alarm_we)
alarm_reg <= alarm_new;
if (key_loaded_we)
key_loaded_reg <= key_loaded_new;
if (fpga_mkm_ctrl_we)
fpga_mkm_ctrl_reg <= fpga_mkm_ctrl_new;
end
//----------------------------------------------------------------
// fpga_mkm_ctrl_fsm
//----------------------------------------------------------------
always @*
begin : fpga_mkm_ctrl_fsm
alarm_new = 1'h0;
alarm_we = 1'h0;
key_loaded_new = 1'h0;
key_loaded_we = 1'h0;
fpga_mkm_ctrl_new = CTRL_IDLE;
fpga_mkm_ctrl_we = 1'h0;
case (fpga_mkm_ctrl_reg)
CTRL_IDLE:
begin
if (tamper)
begin
fpga_mkm_ctrl_new = CTRL_ALARM;
fpga_mkm_ctrl_we = 1'h1;
end
end
CTRL_ALARM:
begin
end
default:
begin
end
endcase // case (fpga_mkm_ctrl_reg)
end
endmodule // fpga_mkm
//======================================================================
// EOF fpga_mkm.v
//======================================================================
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