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2019-03-26Completed first RTL for the SPI slave. Simplified the design to simply be ↵Joachim Strömbergson
two shift registers and a somple FSM that detects clock flanks and SS.
2019-02-12Adding some info about the requirements in the header of the Makefile. This ↵Joachim Strömbergson
could possibly move to the README though...
2019-02-12(1) Fixed Makefile. Now we can build sim target, generate bitstream and also ↵Joachim Strömbergson
burn it to the FPGA dev board. (2) Started structuring the RTL source file.
2019-02-11Fixed Makefile to allow building of simulation executable, linting and FPGA ↵Joachim Strömbergson
bitstream. Updated code to work.