Fixed Makefile to allow building of simulation executable, linting and FPGA bitstream. Updated code to work.

1 files changed, 109 insertions, 0 deletions

diff --git a/toolruns/Makefile b/toolruns/Makefile
new file mode 100755
index 0000000..b95b3cc
--- /dev/null
+++ b/toolruns/Makefile
@@ -0,0 +1,109 @@
+#===================================================================
+#
+# Makefile
+# --------
+# Makefile for building, simlating and programming the the fpga_mkm
+# core. Note that the target device is a Lattice iCEstick
+# Evaluation Kit.
+#
+#
+# Author: Joachim Strombergson
+# Copyright (c) 2019, NORDUnet A/S
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# - Redistributions of source code must retain the above copyright notice,
+#   this list of conditions and the following disclaimer.
+#
+# - Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the distribution.
+#
+# - Neither the name of the NORDUnet nor the names of its contributors may
+#   be used to endorse or promote products derived from this software
+#   without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#===================================================================
+
+# Project defines
+PROJ      = fpga_mkm
+BUILD     = ./build
+DEVICE    = 1k
+FOOTPRINT = tq144
+
+TOP_SRC= ../src/rtl/fpga_mkm.v
+TB_TOP_SRC = ../src/tb/tb_fpga_mkm.v
+CONFIG_SRC= ../src/config/pinmap.pcf
+
+CC = iverilog
+CC_FLAGS = -Wall
+
+LINT = verilator
+LINT_FLAGS = +1364-2001ext+ --lint-only  -Wall -Wno-fatal -Wno-DECLFILENAME
+
+.PHONY: all implement burn
+
+all: top.sim
+
+top.sim: $(TB_TOP_SRC) $(TOP_SRC)
+	$(CC) $(CC_FLAGS) -o top.sim $(TB_TOP_SRC) $(TOP_SRC)
+
+
+sim-top: top.sim
+	./top.sim
+
+
+lint:  $(TOP_SRC)
+	$(LINT) $(LINT_FLAGS) $(TOP_SRC)
+
+
+clean:
+	rm -f *.sim
+	rm build/*
+
+
+implement: $(TOP_SRC)
+	# if build folder doesn't exist, create it
+	mkdir -p $(BUILD)
+	# synthesize using Yosys
+	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(TOP_SRC)
+	# Place and route using arachne
+	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
+	# Convert to bitstream using IcePack
+	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
+
+
+burn:	$(PROJ).bin
+	iceprog $(BUILD)/$(PROJ).bin
+
+
+help:
+	@echo "Build system for simulation of AES Verilog core"
+	@echo ""
+	@echo "Supported targets:"
+	@echo "------------------"
+	@echo "all:          Build all simulation targets."
+	@echo "lint:         Lint all rtl source files."
+	@echo "top.sim:      Build top level simulation target."
+	@echo "sim-top:      Run top level simulation."
+	@echo "implement:    Implement design for the FPGA."
+	@echo "burn:         Write bitstream to FPGA config mem.."
+	@echo "clean:        Delete all built files."
+
+#===================================================================
+# EOF Makefile
+#===================================================================