Age | Commit message (Collapse) | Author | |
---|---|---|---|
2019-04-09 | Adding inital tb for the SPI slave. Debugging the SPI slave and the FPGA_MKM. | Joachim Strömbergson | |
2019-03-26 | Completed first RTL for the SPI slave. Simplified the design to simply be ↵ | Joachim Strömbergson | |
two shift registers and a somple FSM that detects clock flanks and SS. | |||
2019-03-12 | Adding registers, control signals and logic for receiving and transmitting bits. | Joachim Strömbergson | |
2019-03-10 | Adding bit counters for rx and tx. Since they will be updated the same we ↵ | Joachim Strömbergson | |
should have a single counter though. Created rx shift register. | |||
2019-03-07 | Adding initial version of SPI slave interface. So far just defined ports and ↵ | Joachim Strömbergson | |
registers with control signals. |