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+fpga-mkm
+=========
+## Introduction ##
+This core implements a FPGA based, active Master Key Memory (MKM).
+
+The memory provides access control, anti-remanence functionality and
+tamper detection protection with ns zeriosation latency.
+
+The target FPGA family is the Lattice iCE40 that can be kept in stand-by
+with a small battery. The target design flow is the
+[http://www.clifford.at/icestorm/ "Project IceStorm"] fully open source
+Verilog-to-Bitstream flow for iCE40 FPGAs.
+
+The core provides a SPI slave interface for connectivity and one or more
+tamper event inputs. Finally there might be a LED that provides
+status. At least during debugging.
+
+
+
+## Status ##
+Spec is being developed. Core not implemented. Does NOT work.
+
+
+
+## Implementation details
+
+
+
+## Implementation results
+TBW.