(1) Fixed Makefile. Now we can build sim target, generate bitstream and also burn it to the FPGA dev board. (2) Started structuring the RTL source file.

1 files changed, 21 insertions, 9 deletions

diff --git a/src/rtl/fpga_mkm.v b/src/rtl/fpga_mkm.v
index 133a3f8..de96ffa 100644
--- a/src/rtl/fpga_mkm.v
+++ b/src/rtl/fpga_mkm.v
@@ -37,25 +37,37 @@
 //
 //======================================================================
 
-module fpga_mkm (
-                 input wire clk_in,
-                 output wire rled1,
-                 output wire rled2,
-                 output wire rled3,
-                 output wire rled4,
-                 output wire gled5
-                );
+module fpga_mkm(
+                input wire clk_in,
 
+                output wire rled1,
+                output wire rled2,
+                output wire rled3,
+                output wire rled4,
+                output wire gled5
+               );
+
+  //----------------------------------------------------------------
+  // Registers including update variables and write enable.
+  //----------------------------------------------------------------
   reg [31 : 0] counter_reg = 32'b0;
 
+
+  //----------------------------------------------------------------
+  // Concurrent connectivity for ports etc.
+  //----------------------------------------------------------------
   assign rled1 = counter_reg[21];
   assign rled2 = counter_reg[22];
   assign rled3 = counter_reg[23];
   assign rled4 = counter_reg[24];
   assign gled5 = counter_reg[25];
 
+
+  //----------------------------------------------------------------
+  // reg_update
+  //----------------------------------------------------------------
   always @ (posedge clk_in)
-    begin
+    begin : reg_update
       counter_reg <= counter_reg + 1;
     end