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author | Fredrik Thulin <fredrik@thulin.net> | 2017-09-26 12:15:14 +0200 |
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committer | Fredrik Thulin <fredrik@thulin.net> | 2017-09-26 12:15:14 +0200 |
commit | 3af4c15e929f046f955b3222c5f5f1a5ec987ad5 (patch) | |
tree | 21da0b7a0c1746aef5c8992b801caddcacd8d196 | |
parent | a3c49f090d31398e5004c502071c061137874a4e (diff) |
a comment about a difference on layer In2
-rwxr-xr-x | fix-pcb.py | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -133,6 +133,9 @@ def fix_layer_In2_aka_G1(board): that must be connected to GND on other layers, that would easilly get connected with the normal zone parameters. + The current result is missing the connection of the three GND pins on SV1 (FPGA JTAG), but + these three pins are connected on layer In5 aka G2. + Compare with $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In2.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.G1 |