From 3af4c15e929f046f955b3222c5f5f1a5ec987ad5 Mon Sep 17 00:00:00 2001
From: Fredrik Thulin <fredrik@thulin.net>
Date: Tue, 26 Sep 2017 12:15:14 +0200
Subject: a comment about a difference on layer In2

---
 fix-pcb.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fix-pcb.py b/fix-pcb.py
index fb75dc9..939191f 100755
--- a/fix-pcb.py
+++ b/fix-pcb.py
@@ -133,6 +133,9 @@ def fix_layer_In2_aka_G1(board):
     that must be connected to GND on other layers, that would easilly get connected with the
     normal zone parameters.
 
+    The current result is missing the connection of the three GND pins on SV1 (FPGA JTAG), but
+    these three pins are connected on layer In5 aka G2.
+
     Compare with
 
       $ gerbv 'rev03-KiCad/GerberOutput/Cryptech Alpha-In2.Cu.gbr' hardware/production_files/alpha/rev03/Gerbers/CrypTech.G1
-- 
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