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authorFredrik Thulin <fredrik@thulin.net>2017-09-28 13:37:22 +0200
committerFredrik Thulin <fredrik@thulin.net>2017-09-28 13:37:22 +0200
commit392b0e19d13b78387d3528dfba03388acd0ef5bd (patch)
tree6dd1219c1de6a0c0299d7991f576fabd66283958
parent48758ee36d5a3da03cde03c3ef22042d71df2a18 (diff)
add new findings about problems with the schematics
-rw-r--r--README.md7
1 files changed, 6 insertions, 1 deletions
diff --git a/README.md b/README.md
index 998f561..3a40746 100644
--- a/README.md
+++ b/README.md
@@ -17,7 +17,12 @@ NOTE: The latest stable KiCAD version as of this writing is 4.0.7 - it does
NOT include necessary support for stitching vias. Install KiCAD nightly build
to work with the Cryptech Alpha PCB.
-The schematics are successfully converted.
+The schematics are mostly converted. A few components do not connect with their
+nets (e.g. C9 and C10 on sheet rev02_01), but maybe a manual overhaul will be
+needed anyways at the end of conversion. A bigger issue is that no components
+get footprints associated with them in the schema, so generating a new netlist
+won't work at all. The footprints exists in some form in the PCB, so we only
+need to figure out how to reference them properly in the schema.
All the copper layers convert reasonably well. The challenges are mostly
around filled polygons on the various layers. A python script (fix-pcb.py)