From 392b0e19d13b78387d3528dfba03388acd0ef5bd Mon Sep 17 00:00:00 2001 From: Fredrik Thulin Date: Thu, 28 Sep 2017 13:37:22 +0200 Subject: add new findings about problems with the schematics --- README.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 998f561..3a40746 100644 --- a/README.md +++ b/README.md @@ -17,7 +17,12 @@ NOTE: The latest stable KiCAD version as of this writing is 4.0.7 - it does NOT include necessary support for stitching vias. Install KiCAD nightly build to work with the Cryptech Alpha PCB. -The schematics are successfully converted. +The schematics are mostly converted. A few components do not connect with their +nets (e.g. C9 and C10 on sheet rev02_01), but maybe a manual overhaul will be +needed anyways at the end of conversion. A bigger issue is that no components +get footprints associated with them in the schema, so generating a new netlist +won't work at all. The footprints exists in some form in the PCB, so we only +need to figure out how to reference them properly in the schema. All the copper layers convert reasonably well. The challenges are mostly around filled polygons on the various layers. A python script (fix-pcb.py) -- cgit v1.2.3