diff options
author | Fredrik Thulin <fredrik@thulin.net> | 2018-05-09 17:06:28 +0200 |
---|---|---|
committer | Fredrik Thulin <fredrik@thulin.net> | 2018-05-09 17:06:28 +0200 |
commit | 071cd256c55c4ad9b1f8918df2766d141a0da0f2 (patch) | |
tree | 923d9ad0bc2301fd825a811cd9b92df72e7297b2 | |
parent | 96a758c4d6d307be15a132b1e599f524230cfd68 (diff) |
Almost ERC clean. Only three warnings about NotConn sharing pins.
-rwxr-xr-x | add-components.py | 240 | ||||
-rwxr-xr-x | convert.sh | 36 | ||||
-rwxr-xr-x | fix-labels.py | 6 | ||||
-rw-r--r-- | rev03-KiCad/Cryptech_Alpha.lib | 23 | ||||
-rw-r--r-- | rev03-KiCad/rev02_01.sch | 24 | ||||
-rw-r--r-- | rev03-KiCad/rev02_04.sch | 12 | ||||
-rw-r--r-- | rev03-KiCad/rev02_09.sch | 66 | ||||
-rw-r--r-- | rev03-KiCad/rev02_10.sch | 66 | ||||
-rw-r--r-- | rev03-KiCad/rev02_18.sch | 28 | ||||
-rw-r--r-- | rev03-KiCad/rev02_24.sch | 25 |
10 files changed, 480 insertions, 46 deletions
diff --git a/add-components.py b/add-components.py index bc839fa..3dd3d0f 100755 --- a/add-components.py +++ b/add-components.py @@ -28,6 +28,31 @@ def print_lines(fn, out): ' 1 12300 6450', ' 1 0 0 -1 ', '$EndComp', + # Tell KiCad there is power (and GND) in the power jack + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFB973B', + 'P 2200 3300', + 'F 0 "#FLG?" H 2200 3375 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 2200 3474 50 0000 C CNN', + 'F 2 "" H 2200 3300 50 0001 C CNN', + 'F 3 "~" H 2200 3300 50 0001 C CNN', + ' 1 2200 3300', + ' 1 0 0 -1 ', + '$EndComp', + 'Connection ~ 2200 3300', + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFB98AE', + 'P 2200 3500', + 'F 0 "#FLG?" H 2200 3575 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 2200 3673 50 0000 C CNN', + 'F 2 "" H 2200 3500 50 0001 C CNN', + 'F 3 "~" H 2200 3500 50 0001 C CNN', + ' 1 2200 3500', + ' -1 0 0 1 ', + '$EndComp', + 'Connection ~ 2200 3500', ], 'rev02_02.sch': ['NoConn ~ 11500 5200', 'NoConn ~ 4250 6200'], 'rev02_03.sch': ['NoConn ~ 9100 5100', @@ -35,7 +60,19 @@ def print_lines(fn, out): 'NoConn ~ 9100 5300', 'NoConn ~ 6800 5400', 'NoConn ~ 13040 4330'], - 'rev02_04.sch': [], + 'rev02_04.sch': [# Tell KiCad there is power after the R0 resistor on the path to VBATT + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFAF93B', + 'P 2600 4000', + 'F 0 "#FLG?" H 2600 4075 50 0001 C CNN', + 'F 1 "PWR_FLAG" V 2600 4128 50 0000 L CNN', + 'F 2 "" H 2600 4000 50 0001 C CNN', + 'F 3 "~" H 2600 4000 50 0001 C CNN', + ' 1 2600 4000', + ' 0 -1 -1 0 ', + '$EndComp', + 'Connection ~ 2600 4000',], 'rev02_05.sch': ['NoConn ~ 3100 5300', 'NoConn ~ 3100 5400', 'NoConn ~ 3100 5500', @@ -101,7 +138,75 @@ def print_lines(fn, out): 'NoConn ~ 7300 5100', 'NoConn ~ 7300 5000', 'NoConn ~ 7300 4900', - 'NoConn ~ 2000 3600'], + 'NoConn ~ 2000 3600', + '$Comp', + 'L Cryptech_Alpha:FT_VPLL #PWR?', + 'U 1 1 5AF3BF7C', + 'P 7550 2600', + 'F 0 "#PWR?" H 7550 2450 50 0001 C CNN', + 'F 1 "FT_VPLL" V 7565 2727 50 0000 L CNN', + 'F 2 "" H 7550 2600 60 0000 C CNN', + 'F 3 "" H 7550 2600 60 0000 C CNN', + ' 1 7550 2600', + ' 0 -1 -1 0 ', + '$EndComp', + '$Comp', + 'L Cryptech_Alpha:FT_VCC3V3 #PWR?', + 'U 1 1 5AF3CDAF', + 'P 6000 3600', + 'F 0 "#PWR?" H 6000 3450 50 0001 C CNN', + 'F 1 "FT_VCC3V3" V 6015 3728 50 0000 L CNN', + 'F 2 "" H 6000 3600 60 0000 C CNN', + 'F 3 "" H 6000 3600 60 0000 C CNN', + ' 1 6000 3600', + ' 0 -1 -1 0 ', + '$EndComp', + '$Comp', + 'L Cryptech_Alpha:FT_VREGIN #PWR?', + 'U 1 1 5AF3DC52', + 'P 6000 3400', + 'F 0 "#PWR?" H 6000 3250 50 0001 C CNN', + 'F 1 "FT_VREGIN" V 6015 3527 50 0000 L CNN', + 'F 2 "" H 6000 3400 60 0000 C CNN', + 'F 3 "" H 6000 3400 60 0000 C CNN', + ' 1 6000 3400', + ' 0 -1 -1 0 ', + '$EndComp', + '$Comp', + 'L Cryptech_Alpha:FT_VPHY #PWR?', + 'U 1 1 5AF3EA0F', + 'P 7550 2800', + 'F 0 "#PWR?" H 7550 2650 50 0001 C CNN', + 'F 1 "FT_VPHY" V 7565 2927 50 0000 L CNN', + 'F 2 "" H 7550 2800 60 0000 C CNN', + 'F 3 "" H 7550 2800 60 0000 C CNN', + ' 1 7550 2800', + ' 0 -1 -1 0 ', + '$EndComp', + # Tell KiCad there is power after the ferrite bead + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFAEA32', + 'P 8200 7700', + 'F 0 "#FLG?" H 8200 7775 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 8200 7874 50 0000 C CNN', + 'F 2 "" H 8200 7700 50 0001 C CNN', + 'F 3 "~" H 8200 7700 50 0001 C CNN', + ' 1 8200 7700', + ' 1 0 0 -1 ', + '$EndComp', + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFAEB88', + 'P 6400 7700', + 'F 0 "#FLG?" H 6400 7775 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 6400 7874 50 0000 C CNN', + 'F 2 "" H 6400 7700 50 0001 C CNN', + 'F 3 "~" H 6400 7700 50 0001 C CNN', + ' 1 6400 7700', + ' 1 0 0 -1 ', + '$EndComp', + ], 'rev02_10.sch': ['NoConn ~ 9600 4000', 'NoConn ~ 9600 4100', 'NoConn ~ 9600 4200', @@ -118,7 +223,76 @@ def print_lines(fn, out): 'NoConn ~ 2100 3700', 'NoConn ~ 7400 5000', 'NoConn ~ 7400 5100', - 'NoConn ~ 7400 5200'], + 'NoConn ~ 7400 5200', + '$Comp', + 'L Cryptech_Alpha:FT_MGMT_VPLL #PWR?', + 'U 1 1 5AF74540', + 'P 7650 2700', + 'F 0 "#PWR?" H 7650 2550 50 0001 C CNN', + 'F 1 "FT_MGMT_VPLL" V 7665 2827 50 0000 L CNN', + 'F 2 "" H 7650 2700 60 0000 C CNN', + 'F 3 "" H 7650 2700 60 0000 C CNN', + ' 1 7650 2700', + ' 0 -1 -1 0 ', + '$EndComp', + '$Comp', + 'L Cryptech_Alpha:FT_MGMT_VPHY #PWR?', + 'U 1 1 5AF74918', + 'P 7650 2900', + 'F 0 "#PWR?" H 7650 2750 50 0001 C CNN', + 'F 1 "FT_MGMT_VPHY" V 7665 3028 50 0000 L CNN', + 'F 2 "" H 7650 2900 60 0000 C CNN', + 'F 3 "" H 7650 2900 60 0000 C CNN', + ' 1 7650 2900', + ' 0 -1 -1 0 ', + '$EndComp', + '$Comp', + 'L Cryptech_Alpha:FT_MGMT_VREGIN #PWR?', + 'U 1 1 5AF74D26', + 'P 6100 3500', + 'F 0 "#PWR?" H 6100 3350 50 0001 C CNN', + 'F 1 "FT_MGMT_VREGIN" V 6115 3628 50 0000 L CNN', + 'F 2 "" H 6100 3500 60 0000 C CNN', + 'F 3 "" H 6100 3500 60 0000 C CNN', + ' 1 6100 3500', + ' 0 -1 -1 0 ', + '$EndComp', + '$Comp', + 'L Cryptech_Alpha:FT_MGMT_VCC3V3 #PWR?', + 'U 1 1 5AF74F88', + 'P 6100 3700', + 'F 0 "#PWR?" H 6100 3550 50 0001 C CNN', + 'F 1 "FT_MGMT_VCC3V3" V 6115 3828 50 0000 L CNN', + 'F 2 "" H 6100 3700 60 0000 C CNN', + 'F 3 "" H 6100 3700 60 0000 C CNN', + ' 1 6100 3700', + ' 0 -1 -1 0 ', + '$EndComp', + # Tell KiCad there is power after the ferrite bead + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFA8493', + 'P 8300 7800', + 'F 0 "#FLG?" H 8300 7875 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 8300 7974 50 0000 C CNN', + 'F 2 "" H 8300 7800 50 0001 C CNN', + 'F 3 "~" H 8300 7800 50 0001 C CNN', + ' 1 8300 7800', + ' 1 0 0 -1 ', + '$EndComp', + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFA857D', + 'P 6500 7800', + 'F 0 "#FLG?" H 6500 7875 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 6500 7974 50 0000 C CNN', + 'F 2 "" H 6500 7800 50 0001 C CNN', + 'F 3 "~" H 6500 7800 50 0001 C CNN', + ' 1 6500 7800', + ' 1 0 0 -1 ', + '$EndComp', + + ], 'rev02_11.sch': ['NoConn ~ 13200 4300', # Mark BATT pin on JP4 as providing power '$Comp', @@ -334,6 +508,31 @@ def print_lines(fn, out): ' 1 7000 7800', ' 1 0 0 -1', '$EndComp', + # Tell KiCad there is power after the ferrite beads + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFA31D0', + 'P 6050 4800', + 'F 0 "#FLG?" H 6050 4875 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 6050 4974 50 0000 C CNN', + 'F 2 "" H 6050 4800 50 0001 C CNN', + 'F 3 "~" H 6050 4800 50 0001 C CNN', + ' 1 6050 4800', + ' 1 0 0 -1 ', + '$EndComp', + 'Connection ~ 6050 4800', + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFB3F33', + 'P 6050 8000', + 'F 0 "#FLG?" H 6050 8075 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 6050 8174 50 0000 C CNN', + 'F 2 "" H 6050 8000 50 0001 C CNN', + 'F 3 "~" H 6050 8000 50 0001 C CNN', + ' 1 6050 8000', + ' 1 0 0 -1 ', + '$EndComp', + 'Connection ~ 6050 8000', ], 'rev02_19.sch': ['NoConn ~ 1900 5000', 'NoConn ~ 1900 5100', @@ -400,17 +599,30 @@ def print_lines(fn, out): # VCC 1V0 symbol 'Wire Wire Line', ' 8300 6400 8300 6200', - #'$Comp', - #'L Cryptech_Alpha:FPGA_VCCINT_1V0 #PWR?', - #'U 1 1 5AF3F25C', - #'P 8300 6200', - #'F 0 "#PWR?" H 8300 6050 50 0001 C CNN', - #'F 1 "FPGA_VCCINT_1V0" H 8315 6373 50 0000 C CNN', - #'F 2 "" H 8300 6200 60 0000 C CNN', - #'F 3 "" H 8300 6200 60 0000 C CNN', - #' 1 8300 6200', - #' 1 0 0 -1', - #'$EndComp', + '$Comp', + 'L Cryptech_Alpha:FPGA_VCCINT_1V0 #PWR?', + 'U 1 1 5AF3F25C', + 'P 8300 6200', + 'F 0 "#PWR?" H 8300 6050 50 0001 C CNN', + 'F 1 "FPGA_VCCINT_1V0" H 8315 6373 50 0000 C CNN', + 'F 2 "" H 8300 6200 60 0000 C CNN', + 'F 3 "" H 8300 6200 60 0000 C CNN', + ' 1 8300 6200', + ' 1 0 0 -1', + '$EndComp', + # Tell KiCad there is power after the ferrite bead + '$Comp', + 'L power:PWR_FLAG #FLG?', + 'U 1 1 5AFA77EC', + 'P 8150 6400', + 'F 0 "#FLG?" H 8150 6475 50 0001 C CNN', + 'F 1 "PWR_FLAG" H 8150 6574 50 0000 C CNN', + 'F 2 "" H 8150 6400 50 0001 C CNN', + 'F 3 "~" H 8150 6400 50 0001 C CNN', + ' 1 8150 6400', + ' 1 0 0 -1 ', + '$EndComp', + 'Connection ~ 8150 6400', ], 'rev02_25.sch': []} if not comp.get(fn, []): @@ -114,7 +114,7 @@ sed -i -e 's/^X OUT 6 600 300 200 L 70 70 0 1 W$/X OUT 6 600 300 200 L 70 70 0 1 #sed -i -e 's/^X VOUT \(.*\) W$/X VOUT \1 w/g' Cryptech_Alpha.lib # Power jack sed -i \ - -e 's/^X PWR 1 100 300 100 L 1 1 0 1 P$/X PWR 1 100 300 100 L 1 1 0 1 w/' \ + -e 's/^X PWR 1 100 300 100 L 1 1 0 1 P$/X PWR 1 100 300 100 L 1 1 0 1 W/' \ -e 's/^X GND 2 100 100 100 L 1 1 0 1 P$/X GND 2 100 100 100 L 1 1 0 1 W/' \ -e 's/^X GNDBREAK 3 100 200 100 L 1 1 0 1 P$/X GNDBREAK 3 100 200 100 L 1 1 0 1 W/' \ Cryptech_Alpha.lib @@ -130,15 +130,22 @@ sed -i \ sed -i \ -e 's/^X VOUT 5 900 2100 200 L 70 70 0 1 W$/X VOUT 5 900 2100 200 L 70 70 0 1 w/' \ Cryptech_Alpha.lib -# VCCs -#sed -i \ -# -e 's/^X 3V3_BATT 1 0 0 0 U 50 50 1 1 w N$/X 3V3_BATT 1 0 0 0 U 50 50 1 1 W N/' \ -# -e 's/^X FT_VPLL 1 0 0 0 U 50 50 1 1 w N$/X FT_VPLL 1 0 0 0 U 50 50 1 1 W N/' \ -# -e 's/^X FT_VPHY 1 0 0 0 U 50 50 1 1 w N$/X FT_VPHY 1 0 0 0 U 50 50 1 1 W N/' \ -# -e 's/^X FT_VREGIN 1 0 0 0 U 50 50 1 1 w N$/X FT_VREGIN 1 0 0 0 U 50 50 1 1 W N/' \ -# -e 's/^X FT_VCC3V3 1 0 0 0 U 50 50 1 1 w N$/X FT_VCC3V3 1 0 0 0 U 50 50 1 1 W N/' \ -# -e 's/^X FT_VREGIN 1 0 0 0 U 50 50 1 1 w N$/X FT_VREGIN 1 0 0 0 U 50 50 1 1 W N/' \ -# Cryptech_Alpha.lib +# Mark _one_ of the two VOUTs on the LMZ13608 as power output instead of input, since net-ties haven't been used +sed -i \ + -e 's/^X VOUT 10 900 700 200 L 70 70 0 1 W$/X VOUT 10 900 700 200 L 70 70 0 1 w/' \ + Cryptech_Alpha.lib +# FT232H power inputs/outputs +# last letter: +# P = passive +# W = Power input +# w = power output +sed -i \ + -e 's/^X VPHY 3 -200 1500 200 D 70 70 0 1 P/X VPHY 3 -200 1500 200 D 70 70 0 1 W/' \ + -e 's/^X VPLL 8 -100 1500 200 D 70 70 0 1 P/X VPLL 8 -100 1500 200 D 70 70 0 1 W/' \ + -e 's/^X VCCA 37 -1100 800 200 R 70 70 0 1 W/X VCCA 37 -1100 800 200 R 70 70 0 1 w/' \ + -e 's/^X VCCORE 38 -1100 900 200 R 70 70 0 1 W/X VCCORE 38 -1100 900 200 R 70 70 0 1 w/' \ + -e 's/^X VCCD 39 -1100 1000 200 R 70 70 0 1 W/X VCCD 39 -1100 1000 200 R 70 70 0 1 w/' \ + Cryptech_Alpha.lib # Fix off-grid capacitor sed -i \ @@ -183,6 +190,15 @@ grep -vx \ -e 'T 0 -220 -50 50 0 1 1 5% Normal 1 C C' \ -e 'T 0 -220 40 50 0 1 1 5% Normal 1 C C' \ -e 'T 0 -410 420 50 0 1 1 2425618 Normal 1 C C' \ + -e 'T 0 -410 330 50 0 1 1 CONN-08106 Normal 1 C C' \ + -e 'T 0 -410 330 50 0 1 1 PRT-12748 Normal 1 C C' \ + -e 'T 0 -1120 1520 50 0 1 1 1870924 Normal 1 C C' \ + -e 'T 0 -820 910 50 0 1 1 2081146 Normal 1 C C' \ + -e 'T 0 -820 910 50 0 1 1 EN6347QI Normal 1 C C' \ + -e 'T 0 -820 910 50 0 1 1 ENPIRION Normal 1 C C' \ + -e 'T 0 -820 910 50 0 1 1 QFN Normal 1 C C' \ + -e 'T 0 -1220 2320 50 0 1 1 IS45S32160F Normal 1 C C' \ + -e 'T 0 -1220 2320 50 0 1 1 ISSI Normal 1 C C' \ Cryptech_Alpha.lib > Cryptech_Alpha.lib2 mv Cryptech_Alpha.lib2 Cryptech_Alpha.lib diff --git a/fix-labels.py b/fix-labels.py index fa5f823..a00ee12 100755 --- a/fix-labels.py +++ b/fix-labels.py @@ -527,12 +527,12 @@ labels = { 'MKM_FPGA_SCK': [{'t': 'GLabel', 'dir': 'Output', 'x': 2230, 'y': 6400, 'ori': 2, 'new_x': 2950},], }, 'rev02_18.sch': { - 'FPGA_VCCAUX_1V8': [{'t': 'GLabel', 'dir': 'Output', 'x': 6100, 'y': 4800, 'ori': 2, 'new_x': 7000},], + 'FPGA_VCCAUX_1V8': [{'t': 'Label', 'x': 6100, 'y': 4800, 'ori': 2, 'new_x': 7000},], 'POK_VCCAUX': [{'t': 'GLabel', 'dir': 'Output', 'x': 4000, 'y': 6200, 'ori': 2, 'new_y': 6500},], 'POK_VCCO': [{'t': 'GLabel', 'dir': 'Output', 'x': 4000, 'y': 9700, 'ori': 2},], 'PWR_ENA_VCCAUX': [{'t': 'GLabel', 'dir': 'Input', 'x': 1900, 'y': 4740, 'ori': 0, 'new_y': 4150},], 'PWR_ENA_VCCO': [{'t': 'GLabel', 'dir': 'Input', 'x': 1400, 'y': 7500, 'ori': 0},], - 'VCCO_3V3': [{'t': 'Label', 'x': 6100, 'y': 8000, 'ori': 2, 'new_x': 7000},], + 'VCCO_3V3': [{'t': 'Label', 'x': 6100, 'y': 8000, 'ori': 0, 'new_x': 7000},], }, 'rev02_19.sch': { 'AVR_GPIO_FPGA_0': [{'t': 'GLabel', 'dir': 'UnSpc', 'x': 2100, 'y': 8100, 'ori': 2, 'new_x': 3100},], @@ -611,7 +611,7 @@ labels = { 'FPGA_GPIO_LED_3': [{'t': 'GLabel', 'dir': 'Output', 'x': 2470, 'y': 6600, 'ori': 2, 'new_x': 3600},], }, 'rev02_24.sch': { - 'FPGA_VCCINT_1V0': [{'t': 'Label', 'x': 8300, 'y': 6400, 'ori': 2},], + 'FPGA_VCCINT_1V0': [{'t': 'Label', 'x': 8300, 'y': 6400, 'ori': 0},], 'POK_VCCINT': [{'t': 'GLabel', 'dir': 'Output', 'x': 5350, 'y': 9100, 'ori': 2, 'new_x': 5600},], 'PWR_ENA_VCCINT': [{'t': 'GLabel', 'dir': 'Input', 'x': 2700, 'y': 5900, 'ori': 0},], }, diff --git a/rev03-KiCad/Cryptech_Alpha.lib b/rev03-KiCad/Cryptech_Alpha.lib index 1016278..4438f4e 100644 --- a/rev03-KiCad/Cryptech_Alpha.lib +++ b/rev03-KiCad/Cryptech_Alpha.lib @@ -752,7 +752,7 @@ X PGND TP1 -100 -1100 200 U 70 70 0 1 W X FB 7 900 -100 200 L 70 70 0 1 P X SS/TRK 8 -900 -700 200 R 70 70 0 1 P X NC 9 900 -700 200 L 70 70 0 1 P -X VOUT 10 900 700 200 L 70 70 0 1 W +X VOUT 10 900 700 200 L 70 70 0 1 w X VIN 1 -900 700 200 R 70 70 0 1 W X VIN 2 -900 600 200 R 70 70 0 1 W X VOUT 11 900 600 200 L 70 70 0 1 W @@ -792,8 +792,6 @@ F1 "POWER_JACKSMD" -410 -30 60 H V L BNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW -T 0 -410 330 50 0 1 1 CONN-08106 Normal 1 C C -T 0 -410 330 50 0 1 1 PRT-12748 Normal 1 C C P 2 0 1 10 -300 200 -400 100 P 2 0 1 10 -200 100 -300 200 P 2 0 1 10 -100 100 -200 100 @@ -803,7 +801,7 @@ P 2 0 1 10 0 200 -100 200 S -400 270 0 330 0 1 10 f X GNDBREAK 3 100 200 100 L 1 1 0 1 W X GND 2 100 100 100 L 1 1 0 1 W -X PWR 1 100 300 100 L 1 1 0 1 w +X PWR 1 100 300 100 L 1 1 0 1 W ENDDRAW ENDDEF # @@ -1410,8 +1408,6 @@ X DQ14 83 1200 600 100 L 70 70 0 1 P X VSSQ 84 100 -2300 100 U 70 70 0 1 W X DQ15 85 1200 500 100 L 70 70 0 1 P X VSS 86 600 -2300 100 U 70 70 0 1 W -T 0 -1220 2320 50 0 1 1 IS45S32160F Normal 1 C C -T 0 -1220 2320 50 0 1 1 ISSI Normal 1 C C ENDDRAW ENDDEF # @@ -1602,9 +1598,9 @@ P 2 0 1 10 900 -1300 900 1300 P 2 0 1 10 -900 -1300 900 -1300 P 2 0 1 10 -900 1300 -900 -1300 X VREGIN 40 -1100 1200 200 R 70 70 0 1 W -X VCCD 39 -1100 1000 200 R 70 70 0 1 W -X VCCORE 38 -1100 900 200 R 70 70 0 1 W -X VCCA 37 -1100 800 200 R 70 70 0 1 W +X VCCD 39 -1100 1000 200 R 70 70 0 1 w +X VCCORE 38 -1100 900 200 R 70 70 0 1 w +X VCCA 37 -1100 800 200 R 70 70 0 1 w X DM 6 -1100 600 200 R 70 70 0 1 P X DP 7 -1100 500 200 R 70 70 0 1 P X ~RESET 34 -1100 300 200 R 70 70 0 1 P @@ -1644,12 +1640,11 @@ X GND 35 300 -1500 200 U 70 70 0 1 W X GND 36 400 -1500 200 U 70 70 0 1 W X GND 47 500 -1500 200 U 70 70 0 1 W X GND 48 600 -1500 200 U 70 70 0 1 W -X VPHY 3 -200 1500 200 D 70 70 0 1 P -X VPLL 8 -100 1500 200 D 70 70 0 1 P +X VPHY 3 -200 1500 200 D 70 70 0 1 W +X VPLL 8 -100 1500 200 D 70 70 0 1 W X VCCIO 12 0 1500 200 D 70 70 0 1 W X VCCIO 24 100 1500 200 D 70 70 0 1 W X VCCIO 46 200 1500 200 D 70 70 0 1 W -T 0 -1120 1520 50 0 1 1 1870924 Normal 1 C C ENDDRAW ENDDEF # @@ -2630,10 +2625,6 @@ F1 "" 0 0 60 H V C CNN F2 "" 0 0 60 H V C CNN F3 "" 0 0 60 H V C CNN DRAW -T 0 -820 910 50 0 1 1 EN6347QI Normal 1 C C -T 0 -820 910 50 0 1 1 2081146 Normal 1 C C -T 0 -820 910 50 0 1 1 QFN Normal 1 C C -T 0 -820 910 50 0 1 1 ENPIRION Normal 1 C C X NC 1 800 -300 200 L 70 70 0 1 P X NC 2 800 -300 200 L 70 70 0 1 P X NC 3 800 -300 200 L 70 70 0 1 P diff --git a/rev03-KiCad/rev02_01.sch b/rev03-KiCad/rev02_01.sch index caaa6af..7e159df 100644 --- a/rev03-KiCad/rev02_01.sch +++ b/rev03-KiCad/rev02_01.sch @@ -838,4 +838,28 @@ F 3 "" H 12300 6450 60 0000 C CNN 1 12300 6450 1 0 0 -1 $EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFB973B +P 2200 3300 +F 0 "#FLG?" H 2200 3375 50 0001 C CNN +F 1 "PWR_FLAG" H 2200 3474 50 0000 C CNN +F 2 "" H 2200 3300 50 0001 C CNN +F 3 "~" H 2200 3300 50 0001 C CNN + 1 2200 3300 + 1 0 0 -1 +$EndComp +Connection ~ 2200 3300 +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFB98AE +P 2200 3500 +F 0 "#FLG?" H 2200 3575 50 0001 C CNN +F 1 "PWR_FLAG" H 2200 3673 50 0000 C CNN +F 2 "" H 2200 3500 50 0001 C CNN +F 3 "~" H 2200 3500 50 0001 C CNN + 1 2200 3500 + -1 0 0 1 +$EndComp +Connection ~ 2200 3500 $EndSCHEMATC diff --git a/rev03-KiCad/rev02_04.sch b/rev03-KiCad/rev02_04.sch index c3ffe41..bce5104 100644 --- a/rev03-KiCad/rev02_04.sch +++ b/rev03-KiCad/rev02_04.sch @@ -737,4 +737,16 @@ F 3 "" H 12520 4920 60 0000 C CNN 1 12800 5300 1 0 0 -1 $EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFAF93B +P 2600 4000 +F 0 "#FLG?" H 2600 4075 50 0001 C CNN +F 1 "PWR_FLAG" V 2600 4128 50 0000 L CNN +F 2 "" H 2600 4000 50 0001 C CNN +F 3 "~" H 2600 4000 50 0001 C CNN + 1 2600 4000 + 0 -1 -1 0 +$EndComp +Connection ~ 2600 4000 $EndSCHEMATC diff --git a/rev03-KiCad/rev02_09.sch b/rev03-KiCad/rev02_09.sch index 5a6ae29..ec6e848 100644 --- a/rev03-KiCad/rev02_09.sch +++ b/rev03-KiCad/rev02_09.sch @@ -1029,4 +1029,70 @@ NoConn ~ 7300 5100 NoConn ~ 7300 5000 NoConn ~ 7300 4900 NoConn ~ 2000 3600 +$Comp +L Cryptech_Alpha:FT_VPLL #PWR? +U 1 1 5AF3BF7C +P 7550 2600 +F 0 "#PWR?" H 7550 2450 50 0001 C CNN +F 1 "FT_VPLL" V 7565 2727 50 0000 L CNN +F 2 "" H 7550 2600 60 0000 C CNN +F 3 "" H 7550 2600 60 0000 C CNN + 1 7550 2600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_VCC3V3 #PWR? +U 1 1 5AF3CDAF +P 6000 3600 +F 0 "#PWR?" H 6000 3450 50 0001 C CNN +F 1 "FT_VCC3V3" V 6015 3728 50 0000 L CNN +F 2 "" H 6000 3600 60 0000 C CNN +F 3 "" H 6000 3600 60 0000 C CNN + 1 6000 3600 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_VREGIN #PWR? +U 1 1 5AF3DC52 +P 6000 3400 +F 0 "#PWR?" H 6000 3250 50 0001 C CNN +F 1 "FT_VREGIN" V 6015 3527 50 0000 L CNN +F 2 "" H 6000 3400 60 0000 C CNN +F 3 "" H 6000 3400 60 0000 C CNN + 1 6000 3400 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_VPHY #PWR? +U 1 1 5AF3EA0F +P 7550 2800 +F 0 "#PWR?" H 7550 2650 50 0001 C CNN +F 1 "FT_VPHY" V 7565 2927 50 0000 L CNN +F 2 "" H 7550 2800 60 0000 C CNN +F 3 "" H 7550 2800 60 0000 C CNN + 1 7550 2800 + 0 -1 -1 0 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFAEA32 +P 8200 7700 +F 0 "#FLG?" H 8200 7775 50 0001 C CNN +F 1 "PWR_FLAG" H 8200 7874 50 0000 C CNN +F 2 "" H 8200 7700 50 0001 C CNN +F 3 "~" H 8200 7700 50 0001 C CNN + 1 8200 7700 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFAEB88 +P 6400 7700 +F 0 "#FLG?" H 6400 7775 50 0001 C CNN +F 1 "PWR_FLAG" H 6400 7874 50 0000 C CNN +F 2 "" H 6400 7700 50 0001 C CNN +F 3 "~" H 6400 7700 50 0001 C CNN + 1 6400 7700 + 1 0 0 -1 +$EndComp $EndSCHEMATC diff --git a/rev03-KiCad/rev02_10.sch b/rev03-KiCad/rev02_10.sch index ffe7fd1..f84c224 100644 --- a/rev03-KiCad/rev02_10.sch +++ b/rev03-KiCad/rev02_10.sch @@ -1033,4 +1033,70 @@ NoConn ~ 2100 3700 NoConn ~ 7400 5000 NoConn ~ 7400 5100 NoConn ~ 7400 5200 +$Comp +L Cryptech_Alpha:FT_MGMT_VPLL #PWR? +U 1 1 5AF74540 +P 7650 2700 +F 0 "#PWR?" H 7650 2550 50 0001 C CNN +F 1 "FT_MGMT_VPLL" V 7665 2827 50 0000 L CNN +F 2 "" H 7650 2700 60 0000 C CNN +F 3 "" H 7650 2700 60 0000 C CNN + 1 7650 2700 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VPHY #PWR? +U 1 1 5AF74918 +P 7650 2900 +F 0 "#PWR?" H 7650 2750 50 0001 C CNN +F 1 "FT_MGMT_VPHY" V 7665 3028 50 0000 L CNN +F 2 "" H 7650 2900 60 0000 C CNN +F 3 "" H 7650 2900 60 0000 C CNN + 1 7650 2900 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VREGIN #PWR? +U 1 1 5AF74D26 +P 6100 3500 +F 0 "#PWR?" H 6100 3350 50 0001 C CNN +F 1 "FT_MGMT_VREGIN" V 6115 3628 50 0000 L CNN +F 2 "" H 6100 3500 60 0000 C CNN +F 3 "" H 6100 3500 60 0000 C CNN + 1 6100 3500 + 0 -1 -1 0 +$EndComp +$Comp +L Cryptech_Alpha:FT_MGMT_VCC3V3 #PWR? +U 1 1 5AF74F88 +P 6100 3700 +F 0 "#PWR?" H 6100 3550 50 0001 C CNN +F 1 "FT_MGMT_VCC3V3" V 6115 3828 50 0000 L CNN +F 2 "" H 6100 3700 60 0000 C CNN +F 3 "" H 6100 3700 60 0000 C CNN + 1 6100 3700 + 0 -1 -1 0 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA8493 +P 8300 7800 +F 0 "#FLG?" H 8300 7875 50 0001 C CNN +F 1 "PWR_FLAG" H 8300 7974 50 0000 C CNN +F 2 "" H 8300 7800 50 0001 C CNN +F 3 "~" H 8300 7800 50 0001 C CNN + 1 8300 7800 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA857D +P 6500 7800 +F 0 "#FLG?" H 6500 7875 50 0001 C CNN +F 1 "PWR_FLAG" H 6500 7974 50 0000 C CNN +F 2 "" H 6500 7800 50 0001 C CNN +F 3 "~" H 6500 7800 50 0001 C CNN + 1 6500 7800 + 1 0 0 -1 +$EndComp $EndSCHEMATC diff --git a/rev03-KiCad/rev02_18.sch b/rev03-KiCad/rev02_18.sch index 76b9301..e1947c7 100644 --- a/rev03-KiCad/rev02_18.sch +++ b/rev03-KiCad/rev02_18.sch @@ -305,11 +305,11 @@ Wire Wire Line 5500 9000 5500 9200 Wire Wire Line 7000 4800 6000 4800 -Text GLabel 7000 4800 2 48 Output ~ 0 +Text Label 7000 4800 2 48 ~ 0 FPGA_VCCAUX_1V8 Wire Wire Line 7000 8000 6000 8000 -Text Label 7000 8000 2 48 ~ 0 +Text Label 7000 8000 0 48 ~ 0 VCCO_3V3 Wire Wire Line 2100 6200 2100 6300 @@ -788,4 +788,28 @@ F 3 "" H 7000 7800 60 0000 C CNN 1 7000 7800 1 0 0 -1 $EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA31D0 +P 6050 4800 +F 0 "#FLG?" H 6050 4875 50 0001 C CNN +F 1 "PWR_FLAG" H 6050 4974 50 0000 C CNN +F 2 "" H 6050 4800 50 0001 C CNN +F 3 "~" H 6050 4800 50 0001 C CNN + 1 6050 4800 + 1 0 0 -1 +$EndComp +Connection ~ 6050 4800 +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFB3F33 +P 6050 8000 +F 0 "#FLG?" H 6050 8075 50 0001 C CNN +F 1 "PWR_FLAG" H 6050 8174 50 0000 C CNN +F 2 "" H 6050 8000 50 0001 C CNN +F 3 "~" H 6050 8000 50 0001 C CNN + 1 6050 8000 + 1 0 0 -1 +$EndComp +Connection ~ 6050 8000 $EndSCHEMATC diff --git a/rev03-KiCad/rev02_24.sch b/rev03-KiCad/rev02_24.sch index 2a5c73f..94dfe10 100644 --- a/rev03-KiCad/rev02_24.sch +++ b/rev03-KiCad/rev02_24.sch @@ -175,7 +175,7 @@ Wire Wire Line 7600 7400 7600 7600 Wire Wire Line 8300 6400 8100 6400 -Text Label 8300 6400 2 48 ~ 0 +Text Label 8300 6400 0 48 ~ 0 FPGA_VCCINT_1V0 Wire Wire Line 1600 6200 1600 6400 @@ -467,4 +467,27 @@ NoConn ~ 3600 8700 NoConn ~ 5300 8700 Wire Wire Line 8300 6400 8300 6200 +$Comp +L Cryptech_Alpha:FPGA_VCCINT_1V0 #PWR? +U 1 1 5AF3F25C +P 8300 6200 +F 0 "#PWR?" H 8300 6050 50 0001 C CNN +F 1 "FPGA_VCCINT_1V0" H 8315 6373 50 0000 C CNN +F 2 "" H 8300 6200 60 0000 C CNN +F 3 "" H 8300 6200 60 0000 C CNN + 1 8300 6200 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5AFA77EC +P 8150 6400 +F 0 "#FLG?" H 8150 6475 50 0001 C CNN +F 1 "PWR_FLAG" H 8150 6574 50 0000 C CNN +F 2 "" H 8150 6400 50 0001 C CNN +F 3 "~" H 8150 6400 50 0001 C CNN + 1 8150 6400 + 1 0 0 -1 +$EndComp +Connection ~ 8150 6400 $EndSCHEMATC |