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path: root/rtl/src/verilog
AgeCommit message (Expand)Author
2015-02-10First stage of integration cleanup.Paul Selkirk
2015-02-10Updates from Pavel with new mux.Paul Selkirk
2015-02-05add all SHA cores (hello coretest_hashes)Paul Selkirk
2015-02-03(1) Updated core selector with logic to connect sha256. (2) Adding test sw th...Joachim Strömbergson
2015-02-03More attempts at getting the addresss decoder to work...Joachim Strömbergson
2015-02-02Passes build without any warnings.Joachim Strömbergson
2015-02-02Added real prefix detection of sha255 core.Joachim Strömbergson
2015-02-02Changed core_selector to instead use the cryptech sha256 core.Joachim Strömbergson
2015-02-02Changing to Verilog 2001 style interface. Changed port names to not have inpo...Joachim Strömbergson
2015-02-01Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise b...Joachim Strömbergson
2015-02-01Added proper file headers to all verilog source files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and ^M.Joachim Strömbergson
2015-01-31Adding all main hw source files and constraints.Joachim Strömbergson