| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-03-13 | (1) First attempt at connecting the rng core into the novena. (2) Fixed minor... | Joachim Strömbergson |
| 2015-02-10 | Reformat verilog code for readability. | Paul Selkirk |
| 2015-02-10 | Updates from Pavel with new mux. | Paul Selkirk |
| 2015-02-02 | Changing to Verilog 2001 style interface. Changed port names to not have inpo... | Joachim Strömbergson |
| 2015-02-01 | Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise b... | Joachim Strömbergson |
| 2015-02-01 | Added proper file headers to all verilog source files. | Joachim Strömbergson |
| 2015-02-01 | Removed trailing whitespace and ^M. | Joachim Strömbergson |
| 2015-01-31 | Adding all main hw source files and constraints. | Joachim Strömbergson |
 |
index : test/novena_base | |
| Cryptech Novena FPGA baseline | git repositories |
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