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path: root/rtl/src/verilog/novena_baseline_top.v
AgeCommit message (Expand)Author
2015-03-13(1) First attempt at connecting the rng core into the novena. (2) Fixed minor...Joachim Strömbergson
2015-02-10Reformat verilog code for readability.Paul Selkirk
2015-02-10Updates from Pavel with new mux.Paul Selkirk
2015-02-02Changing to Verilog 2001 style interface. Changed port names to not have inpo...Joachim Strömbergson
2015-02-01Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise b...Joachim Strömbergson
2015-02-01Added proper file headers to all verilog source files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and ^M.Joachim Strömbergson
2015-01-31Adding all main hw source files and constraints.Joachim Strömbergson