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2015-02-02Passes build without any warnings.Joachim Strömbergson
2015-02-02Added real prefix detection of sha255 core.Joachim Strömbergson
2015-02-02Changed core_selector to instead use the cryptech sha256 core.Joachim Strömbergson
2015-02-02Changing to Verilog 2001 style interface. Changed port names to not have ↵Joachim Strömbergson
inports called ootput etc. Read and write is better.
2015-02-01Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise ↵Joachim Strömbergson
board. Fixed layout.
2015-02-01Added header with license and info to the constraint file.Joachim Strömbergson
2015-02-01Updated README with more info about the base.Joachim Strömbergson
2015-02-01Changed file type.Joachim Strömbergson
2015-02-01Added proper file headers to all verilog source files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and ^M.Joachim Strömbergson
2015-02-01Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and DOS ^M.Joachim Strömbergson
2015-01-31Adding license for the project.Joachim Strömbergson
2015-01-31Adding all main hw source files and constraints.Joachim Strömbergson
2015-01-31Removed exe bit on source files.Joachim Strömbergson
2015-01-31Adding initial version of the sw parts of the baseline.Joachim Strömbergson
2015-01-31Adding documentation.Joachim Strömbergson
2015-01-31Adding readme to explain the contents of the new repo.Joachim Strömbergson