Added real prefix detection of sha255 core.

1 files changed, 4 insertions, 1 deletions

diff --git a/rtl/src/verilog/core_selector.v b/rtl/src/verilog/core_selector.v
index 7f92e43..092b8ca 100644
--- a/rtl/src/verilog/core_selector.v
+++ b/rtl/src/verilog/core_selector.v
@@ -48,12 +48,15 @@ module core_selector
 	 input wire [31 : 0]  write_data
 	);
 
+  parameter SHA256_BASE = 6'h14;
+  wire is_sha256 = ~(sys_eim_addr[13:8] ^ SHA256_BASE);
+  wire sha256_cs = (is_sha256 & sys_eim_rd) | (is_sha256 & sys_eim_wr);
 
   sha256 sha256_inst(
                      .clk(sys_clk),
                      .reset_n(~sys_rst),
 
-                     .cs(sys_eim_rd | sys_eim_wr),
+                     .cs(sha256_cs),
                      .we(sys_eim_wr),
 
                      .address(sys_eim_addr[7 : 0]),