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2015-02-04Merge branch 'sha256_core' of git.cryptech.is:test/novena_base into sha256_corePaul Selkirk
2015-02-04port hash_tester to this version of novena_eimPaul Selkirk
2015-02-04change 'unsigned int' to the more explicit 'uint32_t'Paul Selkirk
2015-02-04(1) Adding test code to do single block hash. (2) Adding helper function for ↵Joachim Strömbergson
reading data from FPGA registers. (3) Moving eim config to separate function.
2015-02-04Adding NIST test vectors for single and dual block sha256 tests. Adding ↵Joachim Strömbergson
function stubs for tests.
2015-02-04(1) Adding symbols for all registers in the sha256 api.Joachim Strömbergson
2015-02-03(1) Updated core selector with logic to connect sha256. (2) Adding test sw ↵Joachim Strömbergson
that is able to talk to the sha256 core and perform a hash operation.
2015-02-03Adding first base with sha256.Joachim Strömbergson
2015-02-03More attempts at getting the addresss decoder to work...Joachim Strömbergson
2015-02-02Completed first test program for sha256 core.Joachim Strömbergson
2015-02-02Fixed name.Joachim Strömbergson
2015-02-02Adding initial version of test code for sha256 core.Joachim Strömbergson
2015-02-02Passes build without any warnings.Joachim Strömbergson
2015-02-02Added real prefix detection of sha255 core.Joachim Strömbergson
2015-02-02Changed core_selector to instead use the cryptech sha256 core.Joachim Strömbergson
2015-02-02Changing to Verilog 2001 style interface. Changed port names to not have ↵Joachim Strömbergson
inports called ootput etc. Read and write is better.
2015-02-01Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise ↵Joachim Strömbergson
board. Fixed layout.
2015-02-01Added header with license and info to the constraint file.Joachim Strömbergson
2015-02-01Updated README with more info about the base.Joachim Strömbergson
2015-02-01Changed file type.Joachim Strömbergson
2015-02-01Added proper file headers to all verilog source files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and ^M.Joachim Strömbergson
2015-02-01Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.Joachim Strömbergson
2015-02-01Removed trailing whitespace and DOS ^M.Joachim Strömbergson
2015-01-31Adding license for the project.Joachim Strömbergson
2015-01-31Adding all main hw source files and constraints.Joachim Strömbergson
2015-01-31Removed exe bit on source files.Joachim Strömbergson
2015-01-31Adding initial version of the sw parts of the baseline.Joachim Strömbergson
2015-01-31Adding documentation.Joachim Strömbergson
2015-01-31Adding readme to explain the contents of the new repo.Joachim Strömbergson