test/novena_base - Cryptech Novena FPGA baseline

Age	Commit message (Expand)	Author
2015-02-10	Reformat verilog code for readability.	Paul Selkirk
2015-02-10	First stage of integration cleanup.	Paul Selkirk
2015-02-10	Updates from Pavel with new mux.	Paul Selkirk
2015-02-05	add all SHA cores (hello coretest_hashes)	Paul Selkirk
2015-02-04	fix a few warnings and one errorsha256_core	Paul Selkirk
2015-02-04	Merge branch 'sha256_core' of git.cryptech.is:test/novena_base into sha256_core	Paul Selkirk
2015-02-04	port hash_tester to this version of novena_eim	Paul Selkirk
2015-02-04	change 'unsigned int' to the more explicit 'uint32_t'	Paul Selkirk
2015-02-04	(1) Adding test code to do single block hash. (2) Adding helper function for ...	Joachim Strömbergson
2015-02-04	Adding NIST test vectors for single and dual block sha256 tests. Adding funct...	Joachim Strömbergson
2015-02-04	(1) Adding symbols for all registers in the sha256 api.	Joachim Strömbergson
2015-02-03	(1) Updated core selector with logic to connect sha256. (2) Adding test sw th...	Joachim Strömbergson
2015-02-03	Adding first base with sha256.	Joachim Strömbergson
2015-02-03	More attempts at getting the addresss decoder to work...	Joachim Strömbergson
2015-02-02	Completed first test program for sha256 core.	Joachim Strömbergson
2015-02-02	Fixed name.	Joachim Strömbergson
2015-02-02	Adding initial version of test code for sha256 core.	Joachim Strömbergson
2015-02-02	Passes build without any warnings.	Joachim Strömbergson
2015-02-02	Added real prefix detection of sha255 core.	Joachim Strömbergson
2015-02-02	Changed core_selector to instead use the cryptech sha256 core.	Joachim Strömbergson
2015-02-02	Changing to Verilog 2001 style interface. Changed port names to not have inpo...	Joachim Strömbergson
2015-02-01	Changed to Verilog 2001 interface. Added ports for Cryptech avalanche noise b...	Joachim Strömbergson
2015-02-01	Added header with license and info to the constraint file.	Joachim Strömbergson
2015-02-01	Updated README with more info about the base.	Joachim Strömbergson
2015-02-01	Changed file type.	Joachim Strömbergson
2015-02-01	Added proper file headers to all verilog source files.	Joachim Strömbergson
2015-02-01	Removed trailing whitespace and ^M.	Joachim Strömbergson
2015-02-01	Updated the dcm to generate sys_clk at 50 MHz. Added Pavels project files.	Joachim Strömbergson
2015-02-01	Removed trailing whitespace and DOS ^M.	Joachim Strömbergson
2015-01-31	Adding license for the project.	Joachim Strömbergson
2015-01-31	Adding all main hw source files and constraints.	Joachim Strömbergson
2015-01-31	Removed exe bit on source files.	Joachim Strömbergson
2015-01-31	Adding initial version of the sw parts of the baseline.	Joachim Strömbergson
2015-01-31	Adding documentation.	Joachim Strömbergson
2015-01-31	Adding readme to explain the contents of the new repo.	Joachim Strömbergson