diff options
Diffstat (limited to 'sw/novena-eim.h')
| -rw-r--r-- | sw/novena-eim.h | 297 |
1 files changed, 297 insertions, 0 deletions
diff --git a/sw/novena-eim.h b/sw/novena-eim.h new file mode 100644 index 0000000..3d29f77 --- /dev/null +++ b/sw/novena-eim.h @@ -0,0 +1,297 @@ +//------------------------------------------------------------------------------
+// novena-eim.h
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Defined Values
+//------------------------------------------------------------------------------
+#define MEMORY_DEVICE "/dev/mem"
+
+
+//------------------------------------------------------------------------------
+// IOMUXC Values
+//------------------------------------------------------------------------------
+#define IOMUXC_MUX_MODE_ALT0 0 // 000
+
+#define IOMUXC_PAD_CTL_SRE_FAST 1 // 1
+#define IOMUXC_PAD_CTL_DSE_33_OHM 7 // 111
+#define IOMUXC_PAD_CTL_SPEED_MEDIUM_10 2 // 10
+#define IOMUXC_PAD_CTL_ODE_DISABLED 0 // 0
+#define IOMUXC_PAD_CTL_PKE_DISABLED 0 // 0
+#define IOMUXC_PAD_CTL_PUE_PULL 1 // 1
+#define IOMUXC_PAD_CTL_PUS_100K_OHM_PU 2 // 10
+#define IOMUXC_PAD_CTL_HYS_DISABLED 0 // 0
+
+//------------------------------------------------------------------------------
+// CCM Values
+//------------------------------------------------------------------------------
+#define CCM_CGR_OFF 0 // 00
+#define CCM_CGR_ON_EXCEPT_STOP 3 // 11
+
+
+//------------------------------------------------------------------------------
+// CPU Registers
+//------------------------------------------------------------------------------
+enum IMX6DQ_REGISTER_OFFSET
+{
+ IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B = 0x020E00F8,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B = 0x020E0100,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_RW = 0x020E0104,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B = 0x020E0108,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 = 0x020E0114,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 = 0x020E0118,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 = 0x020E011C,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 = 0x020E0120,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 = 0x020E0124,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 = 0x020E0128,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 = 0x020E012C,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 = 0x020E0130,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 = 0x020E0134,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 = 0x020E0138,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 = 0x020E013C,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 = 0x020E0140,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 = 0x020E0144,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 = 0x020E0148,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 = 0x020E014C,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 = 0x020E0150,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B = 0x020E0154,
+ IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK = 0x020E0158,
+
+ IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B = 0x020E040C,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B = 0x020E0414,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_RW = 0x020E0418,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B = 0x020E041C,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 = 0x020E0428,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 = 0x020E042C,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 = 0x020E0430,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 = 0x020E0434,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 = 0x020E0438,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 = 0x020E043C,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 = 0x020E0440,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 = 0x020E0444,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 = 0x020E0448,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 = 0x020E044C,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 = 0x020E0450,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 = 0x020E0454,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 = 0x020E0458,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 = 0x020E045C,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 = 0x020E0460,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 = 0x020E0464,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B = 0x020E0468,
+ IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK = 0x020E046C,
+
+ CCM_CCGR6 = 0x020C4080,
+
+ EIM_CS0GCR1 = 0x021B8000,
+ EIM_CS0GCR2 = 0x021B8004,
+ EIM_CS0RCR1 = 0x021B8008,
+ EIM_CS0RCR2 = 0x021B800C,
+ EIM_CS0WCR1 = 0x021B8010,
+ EIM_CS0WCR2 = 0x021B8014,
+
+ EIM_WCR = 0x021B8090,
+ EIM_WIAR = 0x021B8094,
+ EIM_EAR = 0x021B8098,
+
+ EIM_BASE_ADDR = 0x08000000
+};
+
+
+//------------------------------------------------------------------------------
+struct IOMUXC_SW_MUX_CTL_PAD_EIM
+//------------------------------------------------------------------------------
+{
+ uint32_t mux_mode : 3;
+ uint32_t reserved_3 : 1;
+ uint32_t sion : 1;
+ uint32_t reserved_31_5 : 27;
+};
+//------------------------------------------------------------------------------
+struct IOMUXC_SW_PAD_CTL_PAD_EIM
+//------------------------------------------------------------------------------
+{
+ uint32_t sre : 1;
+ uint32_t reserved_2_1 : 2;
+ uint32_t dse : 3;
+ uint32_t speed : 2;
+ uint32_t reserved_10_8 : 3;
+ uint32_t ode : 1;
+ uint32_t pke : 1;
+ uint32_t pue : 1;
+ uint32_t pus : 2;
+ uint32_t hys : 1;
+ uint32_t reserved_31_17 : 15;
+};
+
+
+//------------------------------------------------------------------------------
+struct CCM_CCGR6
+//------------------------------------------------------------------------------
+{
+ uint32_t cg0_usboh3 : 2;
+ uint32_t cg1_usdhc1 : 2;
+ uint32_t cg2_usdhc2 : 2;
+ uint32_t cg3_usdhc3 : 2;
+
+ uint32_t cg3_usdhc4 : 2;
+ uint32_t cg5_eim_slow : 2;
+ uint32_t cg6_vdoaxiclk : 2;
+ uint32_t cg7_vpu : 2;
+
+ uint32_t cg8_reserved : 2;
+ uint32_t cg9_reserved : 2;
+ uint32_t cg10_reserved : 2;
+ uint32_t cg11_reserved : 2;
+
+ uint32_t cg12_reserved : 2;
+ uint32_t cg13_reserved : 2;
+ uint32_t cg14_reserved : 2;
+ uint32_t cg15_reserved : 2;
+};
+
+
+//------------------------------------------------------------------------------
+struct EIM_CS_GCR1
+//------------------------------------------------------------------------------
+{
+ uint32_t csen : 1;
+ uint32_t swr : 1;
+ uint32_t srd : 1;
+ uint32_t mum : 1;
+ uint32_t wfl : 1;
+ uint32_t rfl : 1;
+ uint32_t cre : 1;
+ uint32_t crep : 1;
+ uint32_t bl : 3;
+ uint32_t wc : 1;
+ uint32_t bcd : 2;
+ uint32_t bcs : 2;
+ uint32_t dsz : 3;
+ uint32_t sp : 1;
+ uint32_t csrec : 3;
+ uint32_t aus : 1;
+ uint32_t gbc : 3;
+ uint32_t wp : 1;
+ uint32_t psz : 4;
+};
+//------------------------------------------------------------------------------
+struct EIM_CS_GCR2
+//------------------------------------------------------------------------------
+{
+ uint32_t adh : 2;
+ uint32_t reserved_3_2 : 2;
+ uint32_t daps : 4;
+ uint32_t dae : 1;
+ uint32_t dap : 1;
+ uint32_t reserved_11_10 : 2;
+ uint32_t mux16_byp_grant : 1;
+ uint32_t reserved_31_13 : 19;
+};
+//------------------------------------------------------------------------------
+struct EIM_CS_RCR1
+//------------------------------------------------------------------------------
+{
+ uint32_t rcsn : 3;
+ uint32_t reserved_3 : 1;
+ uint32_t rcsa : 3;
+ uint32_t reserved_7 : 1;
+ uint32_t oen : 3;
+ uint32_t reserved_11 : 1;
+ uint32_t oea : 3;
+ uint32_t reserved_15 : 1;
+ uint32_t radvn : 3;
+ uint32_t ral : 1;
+ uint32_t radva : 3;
+ uint32_t reserved_23 : 1;
+ uint32_t rwsc : 6;
+ uint32_t reserved_31_30 : 2;
+};
+//------------------------------------------------------------------------------
+struct EIM_CS_RCR2
+//------------------------------------------------------------------------------
+{
+ uint32_t rben : 3;
+ uint32_t rbe : 1;
+ uint32_t rbea : 3;
+ uint32_t reserved_7 : 1;
+ uint32_t rl : 2;
+ uint32_t reserved_11_10 : 2;
+ uint32_t pat : 3;
+ uint32_t apr : 1;
+ uint32_t reserved_31_16 : 16;
+};
+//------------------------------------------------------------------------------
+struct EIM_CS_WCR1
+//------------------------------------------------------------------------------
+{
+ uint32_t wcsn : 3;
+ uint32_t wcsa : 3;
+ uint32_t wen : 3;
+ uint32_t wea : 3;
+ uint32_t wben : 3;
+ uint32_t wbea : 3;
+ uint32_t wadvn : 3;
+ uint32_t wadva : 3;
+ uint32_t wwsc : 6;
+ uint32_t wbed : 1;
+ uint32_t wal : 1;
+};
+//------------------------------------------------------------------------------
+struct EIM_CS_WCR2
+//------------------------------------------------------------------------------
+{
+ uint32_t wbcdd : 1;
+ uint32_t reserved_31_1 : 31;
+};
+//------------------------------------------------------------------------------
+struct EIM_WCR
+//------------------------------------------------------------------------------
+{
+ uint32_t bcm : 1;
+ uint32_t gbcd : 2;
+ uint32_t reserved_3 : 1;
+ uint32_t inten : 1;
+ uint32_t intpol : 1;
+ uint32_t reserved_7_6 : 2;
+ uint32_t wdog_en : 1;
+ uint32_t wdog_limit : 2;
+ uint32_t reserved_31_11 : 21;
+};
+//------------------------------------------------------------------------------
+struct EIM_WIAR
+//------------------------------------------------------------------------------
+{
+ uint32_t ips_req : 1;
+ uint32_t ips_ack : 1;
+ uint32_t irq : 1;
+ uint32_t errst : 1;
+ uint32_t aclk_en : 1;
+ uint32_t reserved_31_5 : 27;
+};
+//------------------------------------------------------------------------------
+struct EIM_EAR
+//------------------------------------------------------------------------------
+{
+ uint32_t error_addr : 32;
+};
+
+
+//------------------------------------------------------------------------------
+// Prototypes
+//------------------------------------------------------------------------------
+int eim_setup ();
+void eim_write_32 (off_t, uint32_t *);
+void eim_read_32 (off_t, uint32_t *);
+
+void _eim_setup_iomuxc ();
+void _eim_setup_ccm ();
+void _eim_setup_eim ();
+void _eim_cleanup ();
+off_t _eim_calc_offset (off_t);
+void _eim_remap_mem (off_t);
+
+
+//------------------------------------------------------------------------------
+// End-of-File
+//------------------------------------------------------------------------------
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