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-rw-r--r--rtl/src/verilog/sha512.v116
1 files changed, 58 insertions, 58 deletions
diff --git a/rtl/src/verilog/sha512.v b/rtl/src/verilog/sha512.v
index 4d2a9e7..8826782 100644
--- a/rtl/src/verilog/sha512.v
+++ b/rtl/src/verilog/sha512.v
@@ -6,7 +6,7 @@
// a simple memory like interface with 32 bit data access.
//
// Authors: Joachim Strömbergson, Paul Selkirk
-// Copyright (c) 2014, NORDUnet A/S All rights reserved.
+// Copyright (c) 2014-2015, NORDUnet A/S All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
@@ -38,15 +38,15 @@
module sha512(
// Clock and reset.
- input wire clk,
- input wire reset_n,
+ input wire clk,
+ input wire reset_n,
// Control.
- input wire cs,
- input wire we,
+ input wire cs,
+ input wire we,
// Data ports.
- input wire [7 : 0] address,
+ input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
@@ -98,12 +98,12 @@ module sha512(
reg [0 : DIGEST_BITS - 1] digest_reg;
reg init_reg;
reg next_reg;
- reg [1 : 0] mode_reg;
- reg work_factor_reg;
- reg [31 : 0] work_factor_num_reg;
+ reg [1 : 0] mode_reg;
+ reg work_factor_reg;
+ reg [31 : 0] work_factor_num_reg;
- reg [31 : 0] tmp_read_data;
- reg [31 : 0] tmp_read_data_reg;
+ reg [31 : 0] tmp_read_data;
+ reg [31 : 0] tmp_read_data_reg;
//----------------------------------------------------------------
// Wires.
@@ -111,9 +111,9 @@ module sha512(
wire core_init;
wire core_next;
wire core_ready;
- wire [1 : 0] core_mode;
- wire core_work_factor;
- wire [31 : 0] core_work_factor_num;
+ wire [1 : 0] core_mode;
+ wire core_work_factor;
+ wire [31 : 0] core_work_factor_num;
wire [0 : BLOCK_BITS - 1] core_block;
wire [0 : DIGEST_BITS - 1] core_digest;
wire core_digest_valid;
@@ -176,66 +176,66 @@ module sha512(
//----------------------------------------------------------------
always @(posedge clk)
begin
- init_reg <= 0;
- next_reg <= 0;
+ init_reg <= 0;
+ next_reg <= 0;
mode_reg <= MODE_SHA_512;
work_factor_reg <= 0;
work_factor_num_reg <= DEFAULT_WORK_FACTOR_NUM;
- if (cs && we)
- begin
- // write operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
- else if (address == ADDR_CTRL)
- begin
- init_reg <= write_data[CTRL_INIT_BIT];
- next_reg <= write_data[CTRL_NEXT_BIT];
+ if (cs && we)
+ begin
+ // write operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ block_reg[((address - ADDR_BLOCK) * 32)+:32] <= write_data;
+ else if (address == ADDR_CTRL)
+ begin
+ init_reg <= write_data[CTRL_INIT_BIT];
+ next_reg <= write_data[CTRL_NEXT_BIT];
mode_reg <= write_data[CTRL_MODE_HIGH_BIT : CTRL_MODE_LOW_BIT];
work_factor_reg <= write_data[CTRL_WORK_FACTOR_BIT];
- end
- else if (address == ADDR_WORK_FACTOR_NUM)
- begin
- work_factor_num_reg <= write_data;
- end
- end
+ end
+ else if (address == ADDR_WORK_FACTOR_NUM)
+ begin
+ work_factor_num_reg <= write_data;
+ end
+ end
end
always @*
begin
- tmp_read_data = 32'h00000000;
-
- if (cs && !we)
- begin
- // read operations
- if ((address >= ADDR_BLOCK) &&
- (address < ADDR_BLOCK + BLOCK_WORDS))
- tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
- else if ((address >= ADDR_DIGEST) &&
- (address < ADDR_DIGEST + DIGEST_WORDS))
- tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
- else
- case (address)
- ADDR_NAME0:
- tmp_read_data = core_name0;
- ADDR_NAME1:
- tmp_read_data = core_name1;
- ADDR_VERSION:
- tmp_read_data = core_version;
- ADDR_CTRL:
- tmp_read_data = core_ctrl;
- ADDR_STATUS:
- tmp_read_data = core_status;
+ tmp_read_data = 32'h00000000;
+
+ if (cs && !we)
+ begin
+ // read operations
+ if ((address >= ADDR_BLOCK) &&
+ (address < ADDR_BLOCK + BLOCK_WORDS))
+ tmp_read_data = block_reg[((address - ADDR_BLOCK) * 32)+:32];
+ else if ((address >= ADDR_DIGEST) &&
+ (address < ADDR_DIGEST + DIGEST_WORDS))
+ tmp_read_data = digest_reg[((address - ADDR_DIGEST) * 32)+:32];
+ else
+ case (address)
+ ADDR_NAME0:
+ tmp_read_data = core_name0;
+ ADDR_NAME1:
+ tmp_read_data = core_name1;
+ ADDR_VERSION:
+ tmp_read_data = core_version;
+ ADDR_CTRL:
+ tmp_read_data = core_ctrl;
+ ADDR_STATUS:
+ tmp_read_data = core_status;
ADDR_WORK_FACTOR_NUM:
tmp_read_data = work_factor_num_reg;
- endcase
- end
+ endcase
+ end
end
always @(posedge clk)
begin
- tmp_read_data_reg <= tmp_read_data;
+ tmp_read_data_reg <= tmp_read_data;
end
endmodule // sha512